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authorXiang, Haihao <haihao.xiang@intel.com>2014-05-26 10:36:49 +0800
committerXiang, Haihao <haihao.xiang@intel.com>2014-06-06 12:40:44 +0800
commitf07cd585c7cf2949826050f2419dd74959155201 (patch)
treeb11284ca8dd44b07765b02975b51323fc87836a9
parent7465b1699cbde5fc6227167d6c28995d947f14f2 (diff)
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VPP: i965_vpp_clear_surface() is still used for CSC on BDW
https://bugs.freedesktop.org/show_bug.cgi?id=79065 The regression is caused by commit 42258e1 Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit 0523c58148e9496927f2c3fa9a641885a0350d0f)
-rwxr-xr-xsrc/i965_post_processing.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/src/i965_post_processing.c b/src/i965_post_processing.c
index 8bdea26..c2db480 100755
--- a/src/i965_post_processing.c
+++ b/src/i965_post_processing.c
@@ -4553,13 +4553,13 @@ i965_vpp_clear_surface(VADriverContextP ctx,
br13 |= BR13_8;
br13 |= pitch;
- if (IS_GEN6(i965->intel.device_info) ||
- IS_GEN7(i965->intel.device_info)) {
- intel_batchbuffer_start_atomic_blt(batch, 48);
- BEGIN_BLT_BATCH(batch, 12);
- } else {
+ if (IS_IRONLAKE(i965->intel.device_info)) {
intel_batchbuffer_start_atomic(batch, 48);
BEGIN_BATCH(batch, 12);
+ } else {
+ /* Will double-check the command if the new chipset is added */
+ intel_batchbuffer_start_atomic_blt(batch, 48);
+ BEGIN_BLT_BATCH(batch, 12);
}
region_width = obj_surface->width;