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2014-08-21radeon: add new SI pci idsAlex Deucher1-0/+4
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-21radeon: add new CIK pci idsAlex Deucher1-0/+3
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-04radeon: Use symbol visibility.Maarten Lankhorst7-69/+98
All the bof_* symbols are now no longer exported. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-07-29radeon: fix typo in sample split / fixes MSAA on HawaiiMarek Olšák1-1/+1
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-07-16radeon: Remove superfluous parentheses.Thomas Klausner1-9/+9
Signed-off-by: Thomas Klausner <wiz@NetBSD.org>
2014-05-02radeon: add Mullins pci idsSamuel Li1-0/+17
Signed-off-by: Samuel Li <samuel.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-05-02radeon: add Mullins chip familySamuel Li1-0/+1
Signed-off-by: Samuel Li <samuel.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2013-12-24radeon: fix sumo2 pci idAlex Deucher1-1/+1
0x9649 is sumo2, not sumo. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-12-24radeon: avoid possible divide by 0 in surface managerAlex Deucher1-3/+3
Some users report hitting a divide by 0 with the tile split in certain apps. Tile_split shouldn't ever be 0 unless the surface structure was not properly initialized. I think there may be some cases where mesa uses an improperly initialized surface struct, but I haven't had time to track it down. Bug: https://bugs.freedesktop.org/show_bug.cgi?id=72425 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2013-11-26radeon: Update unaligned offset for 2D->1D tiling transition on SIMichel Dänzer1-1/+1
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=71983 Tested-by: Arek Ruśniak <arek.rusi@gmail.com>
2013-11-23radeon: handle P16 pipe configs for HawaiiMarek Olšák1-0/+6
2013-11-23radeon: don't overallocate stencil by 4 on SI and CIKMichel Dänzer1-2/+3
Signed-off-by: Marek Olšák <marek.olsak@amd.com> Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com>
2013-11-23radeon: implement 2D tiling for CIKMarek Olšák2-13/+613
Bug fixes and simplification by Marek. We have to use the tile index of 0 for non-MSAA depth-stencil after all. Signed-off-by: Marek Olšák <marek.olsak@amd.com> Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-23radeon: fix mipmap level 0 and 1 alignment for SI and CIKMichel Dänzer1-10/+12
Signed-off-by: Marek Olšák <marek.olsak@amd.com> Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-13radeon: add hawaii pci idsAlex Deucher1-0/+13
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-13radeon: add hawaii chip familyAlex Deucher1-0/+1
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-09-29radeon: fix pitch alignment for non-power-of-two mipmaps on SIMarek Olšák1-3/+11
This fixes VM protection faults. I have a new piglit test which can iterate over all possible widths, heights, and depths (including NPOT) and tests mipmapping with various texture targets. After this is committed, I'll make a new release of libdrm and bump the libdrm version requirement in Mesa.
2013-09-18radeon: Fix tiling mode index for 1D tiled depth/stencil surfaces on CIKMichel Dänzer1-3/+12
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2013-09-06radeon: pad CS to 8 DWAlex Deucher1-0/+3
Aligns the IB to 8 DWs. The aligns the IB to the CP fetch size. r6xx also require at least 4 DW alignment to avoid a hw bug. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-09-06radeon: add berlin pci idsAlex Deucher1-0/+22
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-28radeon: add kabini pci idsAlex Deucher1-0/+17
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-28radeon: add Bonaire pci idsAlex Deucher1-0/+9
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-28radeon: add CIK chip familiesAlex Deucher1-0/+3
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-06radeon: correct RADEON_GEM_WAIT_IDLE useMark Kettenis1-2/+2
RADEON_GEM_WAIT_IDLE is declared DRM_IOW but libdrm uses it with drmCommandWriteRead instead of drmCommandWrite which leads to the ioctl being unmatched and returning an error on at least OpenBSD. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
2013-05-15radeon: add RADEON_SURF_FMASK flag which disables 2D->1D tiling transitionMarek Olšák2-3/+7
Signed-off-by: Marek Olšák <maraeo@gmail.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2013-05-13radeon: add HAINAN pci idsAlex Deucher1-0/+7
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-05-13radeon: add HAINAN familyAlex Deucher1-0/+1
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-04-25radeon: add new richland pci idsAlex Deucher1-0/+2
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-04-25radeon: add new SI pci idsAlex Deucher1-0/+3
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-04-12radeon: add si tiling support v5Jerome Glisse2-45/+644
v2: Only writte tile index if flags for it is set v3: Remove useless allow2d scanout flags v4: Split radeon_drm.h update to its own patch v5: update against lastest next tree for radeon Signed-off-by: Jerome Glisse <jglisse@redhat.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2013-03-08radeon: add pci ids for Richland APUsAlex Deucher1-0/+11
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-03-07radeonsi: make sure tile_split field are not garbageJerome Glisse1-1/+7
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2013-02-04radeon: add OLAND pci idsAlex Deucher1-0/+14
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-02-04radeon: add OLAND familyAlex Deucher1-0/+1
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-01-18radeon: Fix 1D tiling layout on SI.Michel Dänzer1-23/+88
Very similar to Evergreen, but slightly different rules for tile / slice alignment. Fortunately, these map quite naturally onto the previous fixes for linear aligned layout on SI. 2D tiling still needs more work here and possibly in the kernel. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2012-11-28drm/radeon: track global bo name and always return the sameJerome Glisse1-5/+11
To avoid kernel rejecting cs if we return different global name for same bo keep track of global name and always return the same. Seems to fix issue with suspend/resume failing and repeatly printing following message : [drm:radeon_cs_ioctl] *ERROR* Failed to parse relocation -35! There might still be way for a rogue program to trigger this issue. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-11-21radeon: add new SI pci idAlex Deucher1-0/+1
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2012-10-26radeon: fix tile_split of 128-bit surface formats with 8x MSAAMarek Olšák1-0/+2
The calculation led to the number 8192, which is too high. Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-10-24radeon: fix unused-function warningAndreas Boll1-0/+2
radeon_cs_gem.c:333:13: warning: 'cs_gem_dump_bof' defined but not used [-Wunused-function] Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-10-16radeon: add some new SI pci idsAlex Deucher1-0/+3
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-10-06radeon: fix stencil miptree allocation of combined ZS buffers on EG and SIMarek Olšák2-76/+123
This allows texturing with depth-stencil buffers directly without the copy to CB. The separate miptree description for stencil is added, because the stencil mipmap offsets are not really depth offsets/4 (at least for the texture units). Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-10-06radeon: don't force stencil tile split to 0Marek Olšák1-2/+0
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-10-03radeon: don't take the stencil-specific codepath for buffers without stencilMarek Olšák1-1/+1
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-06radeon: Sampling pitch for non-mipmaps seems padded to slice alignment on SI.Michel Dänzer1-3/+8
Another corner case that isn't well-explained yet. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2012-09-06radeon: Memory footprint of SI mipmap base level is padded to powers of two.Michel Dänzer1-3/+10
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2012-09-05radeon: Fix layout of linear aligned mipmaps on SI.Michel Dänzer1-1/+123
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2012-08-24radeon: align r600 msaa buffers to a multiple of macrotile size * num samplesMarek Olšák1-1/+1
I am not sure whether this is needed, but better be safe than sorry.
2012-08-24radeon: fix allocation of MSAA surfaces on r600-r700Marek Olšák1-1/+1
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2012-08-14radeon: add prime import/export supportDave Airlie3-2/+52
this adds radeon version of the prime import/export support. Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-08-09radeon: tweak TILE_SPLIT for MSAA surfacesMarek Olšák1-6/+31
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-26 04:52:06 +0000