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2016-06-27remove the pthread-stub dependencysubmit/tizen/20160627.072623accepted/tizen/wearable/20160629.020052accepted/tizen/tv/20160629.020045accepted/tizen/mobile/20160629.020055accepted/tizen/ivi/20160629.020036accepted/tizen/common/20160701.100325SooChan Lim1-2/+0
Change-Id: I9253557242bb43ec49e4f45eed5d21269bbbb3ac
2014-09-28intel: use drm_mmap/drm_munmap wrappersEmil Velikov2-10/+9
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Reviewed-by: Jakob Bornecrantz <jakob@vmware.com>
2014-09-28automake: pick up all files for distribution.Emil Velikov1-1/+2
Autotools is already smart enough to pick the *.pc.in files but it needs some help with the Android.mk ones. Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Reviewed-by: Jakob Bornecrantz <jakob@vmware.com>
2014-09-19intel: Don't leak the test page in an has_userptr() error pathDamien Lespiau1-3/+2
When handling the error on GEM_CLOSE, we weren't freeing the allocated page. Plug that. Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2014-09-19intel: Adding locks for drm objects synchronization.Rafal Sapala1-4/+24
The changes make sure that members of the bufmgr_gem and bo_gem name lists are sychronized between threads when using the create from prime and create from name methods. Signed-off-by: Rafal Sapala <rafal.a.sapala@intel.com> Testcase: igt/drm_import_export Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-17intel: Add support for userptr objectsTvrtko Ursulin4-1/+193
Allow userptr objects to be created and used via libdrm_intel. At the moment tiling and mapping to GTT aperture is not supported due hardware limitations across different generations and uncertainty about its usefulness. v2: Improved error handling in feature detection per review comments. v3: Rebase on top of the drm_public addition, minor whitespace addition. Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> (v3) Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> (v1,v2)
2014-09-15intel: make drm_intel_gem_bo_get_reloc_count() thread safeLionel Landwerlin1-0/+7
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2014-09-15intel: make bo_unreference() thread safeLionel Landwerlin1-3/+8
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2014-09-15intel: make bufmgr_gem shareable from different APILionel Landwerlin1-5/+58
When using Mesa and LibVA in the same process, one would like to be able bind buffers from the output of the decoder to a GL texture through an EGLImage. LibVA can reuse buffers allocated by Gbm through a file descriptor. It will then wrap it into a drm_intel_bo with drm_intel_bo_gem_create_from_prime(). The problem at the moment is that both library get a different drm_intel_bufmgr object when they call drm_intel_bufmgr_gem_init() even though they're using the same drm file descriptor. As a result, instead of manipulating the same buffer object for a given file descriptor, they get 2 different drm_intel_bo objects and 2 different refcounts, leading one of the library to get errors from the kernel on invalid BO when one of the 2 library is done with a shared buffer. This patch modifies drm_intel_bufmgr_gem_init() so, given a file descriptor, it will look for an already existing drm_intel_bufmgr using the same file descriptor and return that object. Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2014-09-01libdrm,intel: rework android header handlingEmil Velikov1-1/+6
Contains the following patches squashed in: commit 99247a5bd724ddcf0f06a5518baad207c53f1e2b Author: Haitao Huang <haitao.huang@intel.com> Date: Fri, 27 Apr 2012 13:20:53 -0500 Android.mk: use LOCAL_COPY_HEADERS to export headers. Export necessary header files used by other components for Android, such as libva intel-driver, gralloc, hwcomposer, etc. Change-Id: I2feabf6941379ef4d756e942f30eba059de641f1 Signed-off-by: Haitao Huang <haitao.huang@intel.com> [chad: Fixed inconsistent indentation.] Signed-off-by: Chad Versace <chad.versace@linux.intel.com> commit 7d0b528cb69995d7ea4e29b2daa1e3b28a362f42 Author: Emil Velikov <emil.l.velikov@gmail.com> Date: Sun, 27 Jul 2014 18:22:41 +0100 android: reuse headers lists, separate libdrm from intel headers Rather than having a duplicate copy of the headers list(s), reuse the existing one(s). Distinguish that the intel headers should be copied when libdrm_intel is used. v2 Rename the headers variable(s) to *_H_FILES. Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> commit 361de3ba4cadd5357596d1537bb3f216d281532b Author: Piotr Luc <piotr.luc@intel.com> Date: Fri, 14 Jun 2013 13:00:39 +0200 Export include dir from libdrm BZ: 116218 Google introduced new method of specifying include path(s) between modules. This allows a module to include header from a library without directly specifyining by includer the path where headers are located. The method requires from library that holds headers to export include path(s) in LOCAL_EXPORT_C_INCLUDE_DIRS variable. These exported include path(s) are automatically added to include path(s) of modules that have name of the library in the LOCAL_SHARED_LIBRARIES or LOCAL_STATIC_LIBRARIES list. This change sets LOCAL_EXPORT_C_INCLUDE_DIRS to folders that contain headers file that used by other modules in order to export these paths. Change-Id: Id1ac885b31ef2efe194e0289fbcaecd9eb533df0 Signed-off-by: Piotr Luc <piotr.luc@intel.com> Reviewed-on: http://android.intel.com:8080/113562 Reviewed-by: cactus <cactus@intel.com> Reviewed-by: Luc, Piotr <Piotr.Luc@intel.com> Reviewed-by: Purushothaman, Vijay A <vijay.a.purushothaman@intel.com> Reviewed-by: Stimson, Dale B <dale.b.stimson@intel.com> Tested-by: Stimson, Dale B <dale.b.stimson@intel.com> Reviewed-by: buildbot <buildbot@intel.com> Tested-by: buildbot <buildbot@intel.com> commit 2bf22fcbd4cbb9e7c7764d5eff0bb4e75ab1a005 Author: Emil Velikov <emil.l.velikov@gmail.com> Date: 27 Jul 2014 18:27:21 +0100 android: Separate libdrm and intel LOCAL_EXPORT_C_INCLUDE_DIRS Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2014-09-01libdrm,intel: Add Android buildEmil Velikov1-0/+50
Contains the following patches squashed in: commit f340a8b9f2b84d5762553bef046914e0bde20795 Author: Chad Versace <chad.versace@linux.intel.com> Date: Wed, 21 Dec 2011 11:43:57 -0800 libdrm,intel: Add Android makefiles (v2) This enables libdrm.so and libdrm_intel.so to build on Android IceCreamSandwich. v2: Link libdrm_intel to libpciaccess. Change-Id: Ie5ed4bc0e6b4f9f819e3ec44488e385c35e97128 Signed-off-by: Chad Versace <chad.versace@linux.intel.com> commit 8fb3f42389dea34218ed1fe59550ec2abb4d6953 Author: Andrew Boie <andrew.p.boie@intel.com> Date: Wed, 26 Sep 2012 13:32:05 -0700 libdrm, libdrm_intel: Skip driver name checks These libraries have 'optional' tags, which means they won't get built unless something else depends on them or they are added to PRODUCT_PACKAGES. There's no need for additional filtering. Change-Id: I5d90969f38671f8144c0dc27d47144b3f09a15ce Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2014-09-01libdrm, freedreno, intel, nouveau, radeon: add Makefile.sourcesEmil Velikov2-12/+18
Will be used to consolidate the required sources lists as well as the install-able headers. This is turn will help us to avoid the duplication with the upcoming Android build support. v2: Rename the headers variable to *_H_FILES. v3: Rebase on top of symbol visibility patches. Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2014-09-01all: include config.h only when available and use its definesEmil Velikov1-2/+3
... rather than explicitly redefining HAVE_STDINT_H and _GNU_SOURCE. Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2014-08-04intel: Use symbol visibility.Maarten Lankhorst5-83/+114
No exports changed for this driver. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-04-29intel/chv: Add Cherryview PCI IDsVille Syrjälä1-1/+11
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
2014-04-17intel: Fix some format stringsThierry Reding1-10/+10
Some of the format strings for debug messages use the wrong modifier to print sizes. Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-04-17Mark functions printf-like where possibleThierry Reding1-5/+2
These functions all take a format string and either a list of variable arguments or a va_list. Use the new DRM_PRINTFLIKE macro to tell the compiler about it so that the arguments can be checked against the format string. Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-01-20intel: Create a new drm_intel_bo offset64 field.Kenneth Graunke2-9/+19
The existing 'offset' field is unfortunately typed as 'unsigned long', which is unfortunately only 4 bytes with a 32-bit userspace. Traditionally, the hardware has only supported 32-bit virtual addresses, so even though the kernel uses a __u64, the value would always fit. However, Broadwell supports 48-bit addressing. So with a 64-bit kernel, the card virtual address may be too large to fit in the 'offset' field. Ideally, we would change the type of 'offset' to be a uint64_t---but this would break the libdrm ABI. Instead, we create a new 'offset64' field to hold the full 64-bit value from the kernel, and store the 32-bit truncation in the existing 'offset' field, for compatibility. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-01-20intel: Track whether a buffer is idle to avoid trips to the kernel.Eric Anholt1-1/+22
I've seen a number of apps spending unreasonable amounts of time in drm_intel_bo_busy during the buffer mapping process. We can't track idleness in general, in the case of buffers shared across processes. But this should significantly reduce our overhead for checking for busy on things like VBOs. Improves (unoptimized) glamor x11perf -f8text by 0.243334% +/- 0.161498% (n=1549), which has formerly been spending about .5% of its time hitting the kernel for drm_intel_gem_bo_busy(). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-01-10intel: Handle malloc fails in context createBen Widawsky1-1/+5
The previous code would just use the potentially unallocated variable, which is probably okay most of the time, but not very nice to the user of the library. Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2014-01-10intel: squash unused variable 'bo_gem'Ben Widawsky1-0/+2
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-12-13intel/test_decode: Allow gen8 to be infered from the batch filenamesDamien Lespiau1-0/+1
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-11-26 intel: Track known prime buffers for re-useKeith Packard1-7/+43
If the application sends us a file descriptor pointing at a prime buffer that we've already got, we have to re-use the same bo_gem structure or chaos will result. Track the set of all known prime objects and look to see if the kernel has returned one of those for a new file descriptor. Also checks for prime buffers in the flink case. Signed-off-by: Keith Packard <keithp@keithp.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-20intel: Use memset instead of VG_CLEARIan Romanick1-1/+1
The ioctl expects that certain fields will be zeroed, so we should allow the helper function to actually work in non-Valgrind builds. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reported-by: Zhenyu Wang <zhenyuw@linux.intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-15intel: Add support for GPU reset status query ioctlIan Romanick2-0/+39
I would have just used the drmIoctl interface directly in Mesa, but the ioctl needs some data from the drm_intel_context that is not exposed outside libdrm. This ioctl is in the drm-intel-next tree as b635991. v2: Update based on Mika's kernel work. v3: Fix compile failures from last-minute typos. Sigh. v4: Import the actual changes from the kernel i915_drm.h. Only comments on some fields of drm_i915_reset_stats differed. There are still some deltas between the kernel i915_drm.h and the one in libdrm, but those can be resolved in other patches. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> [v3] Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Cc: Mika Kuoppala <mika.kuoppala@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08Revert "intel: Add support for GPU reset status query ioctl"Dave Airlie2-39/+0
This reverts commit 6335e1d28c422050024bcf4100c4fb3a5bac2afb. No taxation without representation, in other words no userspace without kernel stuff being in a stable location, either drm-next but I'll accept drm-intel-next for intel specific stuff.
2013-11-07intel: Add support for GPU reset status query ioctlIan Romanick2-0/+39
I would have just used the drmIoctl interface directly in Mesa, but the ioctl needs some data from the drm_intel_context that is not exposed outside libdrm. v2: Update based on Mika's kernel work. v3: Fix compile failures from last-minute typos. Sigh. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Cc: Mika Kuoppala <mika.kuoppala@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-07intel/bdw: Update MI_BATCH_BUFFER_START for aub dumpsDamien Lespiau1-2/+8
The command now takes a 48bits address and is thus 1 dword longer. v2 (Ben): commit message: s/byte/dword (Eric) Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-07intel/bdw/aub: Update AUB trace block writes for 48-bit addressing.Kenneth Graunke1-3/+9
Since our aub file dumping's GTT handling is totally fake, we always put everything in the low 4GB anyway and shouldn't ever need to set AddressHigh to anything other than 0. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> [ben: slight commit message change] Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-07intel/bdw: Add gen8 to the decode initDamien Lespiau1-1/+3
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-07intel/bdw: Handle gen8 bufmgr_initBen Widawsky1-0/+2
[bwidawsk: Added Damien's SOB] Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-07intel/bdw: Add broadwell chipset IDsBen Widawsky1-1/+21
v2: Rename s/<SECRET>/IRIS/ Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-10-29intel: Add MI_LOAD_REGISTER_MEM to intel_decode.c.Kenneth Graunke1-0/+1
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
2013-10-29intel: Add the Gen6+ version of MI_REPORT_PERF_COUNT to intel_decode.c.Kenneth Graunke1-0/+1
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
2013-10-10intel: Set bo size from lseek if kernel supports itKristian Høgsberg1-1/+11
The various create and open functions set the buffer size, but drm_intel_bo_gem_create_from_prime() is an exception. In the 3.12 kernel we can now use lseek on the prime fd to determine the size of the bo. Use that and override the userprovided size. If the kernel doesn't support this, we get an error and fall back to the user provided size. Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
2013-08-30intel: Update package name and description in libdrm_intel.pcEmil Velikov1-2/+2
Currently the package name and description duplicate that of the core libdrm. Update those to reflect reality. Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
2013-07-16intel: silence valgrind warnings for unsynchronized mapsChia-I Wu1-0/+7
Mark the address ranges as accessible with VALGRIND_MAKE_MEM_DEFINED. Signed-off-by: Chia-I Wu <olvaffe@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-06-10intel/aub: Implement a way to specify the output .aub filenameDamien Lespiau2-1/+28
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-06-10intel/aub: Return early if we disable aub dumpsDamien Lespiau1-0/+1
No need to prepare the .aub header and dump in that case, it'll be done with the next call with true. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-06-10intel/aub: Sync the AUB defines with mesa'sDamien Lespiau1-23/+53
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-06-05intel: Adding more reserved PCI IDs for Haswell.Rodrigo Vivi1-3/+51
At DDX commit Chris mentioned the tendency we have of finding out more PCI IDs only when users report. So Let's add all new reserved Haswell IDs. Bugzilla: http://bugs.freedesktop.org/show_bug.cgi?id=63701 Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2013-06-05intel: Fix Haswell GT3 names.Rodrigo Vivi1-26/+27
When publishing first HSW ids we weren't allowed to use "GT3" codname. But this is the correct codname and Mesa is using it already. So to avoid people getting confused why in Mesa it is called GT3 and here it is called GT2_PLUS let's fix this name in a standard and correct way. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Reviewed-by: Chad Versace <chad.versace@linux.intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-04-27intel: Add support for VEBOX ring (v2)Xiang, Haihao1-0/+9
v2: Fix the test for has_vebox Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-04-04intel-decode: Fix gen6 HIER_DEPTH_BUFFER decodingDaniel Vetter2-4/+4
It accidentally used the cmd id for the gen7 command and had an outdated lenght field. Spotted while trying to make sense of an ivb error_state from mesa 7.11 ... Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-03-28intel: Fix Haswell CRW PCI IDs.Kenneth Graunke1-9/+9
The second digit was off by one, which meant we accidentally treated GT(n) as GT(n-1). This also meant no support for GT1 at all. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-27intel_chipset: Fix up VLV confusionVille Syrjälä1-3/+3
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
2013-03-27intel_chipset: Use parens around macro argumentsVille Syrjälä1-155/+155
Protect the macro argument evaluations with parens. This is already touching most lines, so while at it, fix up all white space to uniform style throughout the file. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
2013-02-11intel_chipset: Merge intel-gpu-tools chipsetsBen Widawsky1-75/+101
Intel GPU Tools is newer and arguably better. This change doesn't completely merge the files because it's a bit simpler if we move the I9XX macro over to Intel GPU Tools, and don't move over a few macros from IGT that libdrm doesn't care about. It has been discussed, and would seem even easier if Intel GPU Tools simply used the libdrm header files. Whether or not we move to that, this should help that effort. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2013-02-06intel: fix length mask for Gen5/Gen6 3DSTATE_CLEAR_PARAMSupstream/2.4.45Chris Forbes1-1/+1
On Gen6, bit 15 is now `Depth Clear Value Valid`. This was being treated as part of the length, and failing the rest of the batchbuffer decode. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
2013-02-06intel/aub: Actually run BLT batches on the blit ring.Kenneth Graunke1-0/+2
We didn't set the ring flag for BLT batches, so they got run on the render ring. Shenanigans ensued, especially when we sent commands that were only valid on the BLT ring. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
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