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| author | Alex Deucher <alexander.deucher@amd.com> | 2016-02-19 19:22:51 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2016-05-13 15:10:01 -0400 |
| commit | b7a51965e1c7a6e988c4882254ca21aa184f6396 (patch) | |
| tree | 2986f4a4456ecfbb698cc77e8b655279ca275653 /tests | |
| parent | fc09c5ab84240e9b6bd0bed01685ef004f56c4fa (diff) | |
| download | libdrm-b7a51965e1c7a6e988c4882254ca21aa184f6396.tar.gz libdrm-b7a51965e1c7a6e988c4882254ca21aa184f6396.tar.bz2 libdrm-b7a51965e1c7a6e988c4882254ca21aa184f6396.zip | |
tests/amdgpu: expand write/copy tests to compute
Uses same packets as gfx.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/amdgpu/basic_tests.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c index 599c090a..05ab1459 100644 --- a/tests/amdgpu/basic_tests.c +++ b/tests/amdgpu/basic_tests.c @@ -813,7 +813,8 @@ static void amdgpu_command_submission_write_linear_helper(unsigned ip_type) pm4[i++] = sdma_write_length; while(j++ < sdma_write_length) pm4[i++] = 0xdeadbeaf; - } else if (ip_type == AMDGPU_HW_IP_GFX) { + } else if ((ip_type == AMDGPU_HW_IP_GFX) || + (ip_type == AMDGPU_HW_IP_COMPUTE)) { pm4[i++] = PACKET3(PACKET3_WRITE_DATA, 2 + sdma_write_length); pm4[i++] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; pm4[i++] = 0xfffffffc & bo_mc; @@ -911,7 +912,8 @@ static void amdgpu_command_submission_const_fill_helper(unsigned ip_type) pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; pm4[i++] = 0xdeadbeaf; pm4[i++] = sdma_write_length; - } else if (ip_type == AMDGPU_HW_IP_GFX) { + } else if ((ip_type == AMDGPU_HW_IP_GFX) || + (ip_type == AMDGPU_HW_IP_COMPUTE)) { pm4[i++] = PACKET3(PACKET3_DMA_DATA, 5); pm4[i++] = PACKET3_DMA_DATA_ENGINE(0) | PACKET3_DMA_DATA_DST_SEL(0) | @@ -1030,7 +1032,8 @@ static void amdgpu_command_submission_copy_linear_helper(unsigned ip_type) pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32; pm4[i++] = 0xffffffff & bo2_mc; pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; - } else if (ip_type == AMDGPU_HW_IP_GFX) { + } else if ((ip_type == AMDGPU_HW_IP_GFX) || + (ip_type == AMDGPU_HW_IP_COMPUTE)) { pm4[i++] = PACKET3(PACKET3_DMA_DATA, 5); pm4[i++] = PACKET3_DMA_DATA_ENGINE(0) | PACKET3_DMA_DATA_DST_SEL(0) | |