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author | Jerome Glisse <jglisse@redhat.com> | 2012-02-13 20:45:53 -0500 |
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committer | Jerome Glisse <jglisse@redhat.com> | 2012-02-13 20:46:43 -0500 |
commit | 9b3ad51ae5fd9654df8ef75de845a519015150bb (patch) | |
tree | a28b5e5274a4e14fa2c589462977dd312e808445 /radeon | |
parent | ced219ebbd3b266ac8326223bad62f994907ae6b (diff) | |
download | libdrm-9b3ad51ae5fd9654df8ef75de845a519015150bb.tar.gz libdrm-9b3ad51ae5fd9654df8ef75de845a519015150bb.tar.bz2 libdrm-9b3ad51ae5fd9654df8ef75de845a519015150bb.zip |
radeon: fix pitch alignment for scanout buffer
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Diffstat (limited to 'radeon')
-rw-r--r-- | radeon/radeon_surface.c | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c index d7e91872..94224f5e 100644 --- a/radeon/radeon_surface.c +++ b/radeon/radeon_surface.c @@ -243,9 +243,12 @@ static int r6_surface_init_linear(struct radeon_surface_manager *surf_man, /* the 32 alignment is for scanout, cb or db but to allow texture to be * easily bound as such we force this alignment to all surface */ - xalign = MAX2(32, surf_man->hw_info.group_bytes / surf->bpe); + xalign = MAX2(1, surf_man->hw_info.group_bytes / surf->bpe); yalign = 1; zalign = 1; + if (surf->flags & RADEON_SURF_SCANOUT) { + xalign = MAX2((surf->bpe == 1) ? 64 : 32, xalign); + } /* build mipmap tree */ for (i = start_level; i <= surf->last_level; i++) { @@ -301,6 +304,9 @@ static int r6_surface_init_1d(struct radeon_surface_manager *surf_man, xalign = MAX2(tilew, xalign); yalign = tilew; zalign = 1; + if (surf->flags & RADEON_SURF_SCANOUT) { + xalign = MAX2((surf->bpe == 1) ? 64 : 32, xalign); + } if (!start_level) { surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes); } @@ -332,6 +338,9 @@ static int r6_surface_init_2d(struct radeon_surface_manager *surf_man, (tilew * surf->bpe * surf->nsamples); xalign = MAX2(tilew * surf_man->hw_info.num_banks, xalign); yalign = tilew * surf_man->hw_info.num_pipes; + if (surf->flags & RADEON_SURF_SCANOUT) { + xalign = MAX2((surf->bpe == 1) ? 64 : 32, xalign); + } if (!start_level) { surf->bo_alignment = MAX2(surf_man->hw_info.num_pipes * @@ -545,6 +554,9 @@ static int eg_surface_init_1d(struct radeon_surface_manager *surf_man, xalign = MAX2(tilew, xalign); yalign = tilew; zalign = 1; + if (surf->flags & RADEON_SURF_SCANOUT) { + xalign = MAX2((surf->bpe == 1) ? 64 : 32, xalign); + } if (!start_level) { surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes); } |