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| author | José Roberto de Souza <jose.souza@intel.com> | 2018-06-19 16:45:21 -0700 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2018-06-20 16:39:53 -0700 |
| commit | 7164abebecfbf450cdc55133eb3162f8c1501ff3 (patch) | |
| tree | 385fb601ab965bcfc8ce4f707b1e2bd50f52eb03 /intel | |
| parent | 591c1d72abbc1ae67890a50dc107a0e4b9ef13c3 (diff) | |
| download | libdrm-7164abebecfbf450cdc55133eb3162f8c1501ff3.tar.gz libdrm-7164abebecfbf450cdc55133eb3162f8c1501ff3.tar.bz2 libdrm-7164abebecfbf450cdc55133eb3162f8c1501ff3.zip | |
intel: Introducing Amber Lake platform
Amber Lake uses the same gen graphics as Kaby Lake, including a id
that were previously marked as reserved on Kaby Lake, but that now is
moved to AML page.
So, let's just move it to AML macro that will feed into KBL macro
just to keep it better organized to make easier future code review
but it will be handled as a KBL.
This is a copy of merged i915's
commit e364672477a1 ("drm/i915/aml: Introducing Amber Lake platform")
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'intel')
| -rw-r--r-- | intel/intel_chipset.h | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h index 44e65f9e..583d6447 100644 --- a/intel/intel_chipset.h +++ b/intel/intel_chipset.h @@ -201,7 +201,6 @@ #define PCI_CHIP_KABYLAKE_ULX_GT1_5 0x5915 #define PCI_CHIP_KABYLAKE_ULX_GT1 0x590E #define PCI_CHIP_KABYLAKE_ULX_GT2_0 0x591E -#define PCI_CHIP_KABYLAKE_ULX_GT2_1 0x591C #define PCI_CHIP_KABYLAKE_DT_GT2 0x5912 #define PCI_CHIP_KABYLAKE_M_GT2 0x5917 #define PCI_CHIP_KABYLAKE_DT_GT1 0x5902 @@ -213,6 +212,9 @@ #define PCI_CHIP_KABYLAKE_SRV_GT1 0x590A #define PCI_CHIP_KABYLAKE_WKS_GT2 0x591D +#define PCI_CHIP_AMBERLAKE_ULX_GT2_1 0x591C +#define PCI_CHIP_AMBERLAKE_ULX_GT2_2 0x87C0 + #define PCI_CHIP_BROXTON_0 0x0A84 #define PCI_CHIP_BROXTON_1 0x1A84 #define PCI_CHIP_BROXTON_2 0x5A84 @@ -468,12 +470,13 @@ #define IS_KBL_GT2(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT2 || \ (devid) == PCI_CHIP_KABYLAKE_ULT_GT2F || \ (devid) == PCI_CHIP_KABYLAKE_ULX_GT2_0 || \ - (devid) == PCI_CHIP_KABYLAKE_ULX_GT2_1 || \ (devid) == PCI_CHIP_KABYLAKE_DT_GT2 || \ (devid) == PCI_CHIP_KABYLAKE_M_GT2 || \ (devid) == PCI_CHIP_KABYLAKE_HALO_GT2 || \ (devid) == PCI_CHIP_KABYLAKE_SRV_GT2 || \ - (devid) == PCI_CHIP_KABYLAKE_WKS_GT2) + (devid) == PCI_CHIP_KABYLAKE_WKS_GT2 || \ + (devid) == PCI_CHIP_AMBERLAKE_ULX_GT2_1 || \ + (devid) == PCI_CHIP_AMBERLAKE_ULX_GT2_2) #define IS_KBL_GT3(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT3_0 || \ (devid) == PCI_CHIP_KABYLAKE_ULT_GT3_1 || \ |