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authorKenneth Graunke <kenneth@whitecape.org>2013-10-29 19:30:45 -0700
committerKenneth Graunke <kenneth@whitecape.org>2013-10-29 20:57:02 -0700
commit551aac43750714bded31f9331da0b13280cc5832 (patch)
tree5c39600f80c3933c14a58a7ad4725d58a51e772b /intel
parent951ebe0081bd2e15bc7685f07fa3318fa5bccfad (diff)
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intel: Add the Gen6+ version of MI_REPORT_PERF_COUNT to intel_decode.c.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
Diffstat (limited to 'intel')
-rw-r--r--intel/intel_decode.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/intel/intel_decode.c b/intel/intel_decode.c
index ff19f92e..5bf0aff4 100644
--- a/intel/intel_decode.c
+++ b/intel/intel_decode.c
@@ -257,6 +257,7 @@ decode_mi(struct drm_intel_decode *ctx)
{ 0x03, 0, 1, 1, "MI_WAIT_FOR_EVENT", decode_MI_WAIT_FOR_EVENT },
{ 0x16, 0x7f, 3, 3, "MI_SEMAPHORE_MBOX" },
{ 0x26, 0x1f, 3, 4, "MI_FLUSH_DW" },
+ { 0x28, 0x3f, 3, 3, "MI_REPORT_PERF_COUNT" },
{ 0x0b, 0, 1, 1, "MI_SUSPEND_FLUSH"},
}, *opcode_mi = NULL;