diff options
| author | Hyungwon Hwang <human.hwang@samsung.com> | 2014-09-02 16:58:30 +0900 |
|---|---|---|
| committer | Quanxian Wang <quanxian.wang@intel.com> | 2014-10-15 12:07:07 +0800 |
| commit | d282c25d7098b5dc346baed5551e7e3ec618414c (patch) | |
| tree | 80094191b8eb342de8e6394b477cb64a3545adb6 /exynos | |
| parent | c9a8bb234df83a94424ccf9371551a184c45e361 (diff) | |
| download | libdrm-d282c25d7098b5dc346baed5551e7e3ec618414c.tar.gz libdrm-d282c25d7098b5dc346baed5551e7e3ec618414c.tar.bz2 libdrm-d282c25d7098b5dc346baed5551e7e3ec618414c.zip | |
libdrm/exynos: add support for IPP blending, dithering, and colorfill
This patch adds the fields for IPP bleding, dithering, and colorfill.
Change-Id: Ib9cd7c7b22ee9f1017d1db3ae34d39dea342ffec
Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
Diffstat (limited to 'exynos')
| -rw-r--r-- | exynos/exynos_drm.h | 66 |
1 files changed, 63 insertions, 3 deletions
diff --git a/exynos/exynos_drm.h b/exynos/exynos_drm.h index b1281961..e7e7f6e3 100644 --- a/exynos/exynos_drm.h +++ b/exynos/exynos_drm.h @@ -209,6 +209,57 @@ enum drm_exynos_planer { EXYNOS_DRM_PLANAR_MAX, }; +/* define of blending operation */ +enum drm_exynos_ipp_blending { + IPP_BLENDING_NO, + /* [0, 0] */ + IPP_BLENDING_CLR, + /* [Sa, Sc] */ + IPP_BLENDING_SRC, + /* [Da, Dc] */ + IPP_BLENDING_DST, + /* [Sa + (1 - Sa)*Da, Rc = Sc + (1 - Sa)*Dc] */ + IPP_BLENDING_SRC_OVER, + /* [Sa + (1 - Sa)*Da, Rc = Dc + (1 - Da)*Sc] */ + IPP_BLENDING_DST_OVER, + /* [Sa * Da, Sc * Da] */ + IPP_BLENDING_SRC_IN, + /* [Sa * Da, Sa * Dc] */ + IPP_BLENDING_DST_IN, + /* [Sa * (1 - Da), Sc * (1 - Da)] */ + IPP_BLENDING_SRC_OUT, + /* [Da * (1 - Sa), Dc * (1 - Sa)] */ + IPP_BLENDING_DST_OUT, + /* [Da, Sc * Da + (1 - Sa) * Dc] */ + IPP_BLENDING_SRC_ATOP, + /* [Sa, Sc * (1 - Da) + Sa * Dc ] */ + IPP_BLENDING_DST_ATOP, + /* [-(Sa * Da), Sc * (1 - Da) + (1 - Sa) * Dc] */ + IPP_BLENDING_XOR, + /* [Sa + Da - Sa*Da, Sc*(1 - Da) + Dc*(1 - Sa) + min(Sc, Dc)] */ + IPP_BLENDING_DARKEN, + /* [Sa + Da - Sa*Da, Sc*(1 - Da) + Dc*(1 - Sa) + max(Sc, Dc)] */ + IPP_BLENDING_LIGHTEN, + /* [Sa * Da, Sc * Dc] */ + IPP_BLENDING_MULTIPLY, + /* [Sa + Da - Sa * Da, Sc + Dc - Sc * Dc] */ + IPP_BLENDING_SCREEN, + /* Saturate(S + D) */ + IPP_BLENDING_ADD, + /* Max */ + IPP_BLENDING_MAX, +}; + +/* define of dithering operation */ +enum drm_exynos_ipp_dithering { + IPP_DITHERING_NO, + IPP_DITHERING_8BIT, + IPP_DITHERING_6BIT, + IPP_DITHERING_5BIT, + IPP_DITHERING_4BIT, + IPP_DITHERING_MAX, +}; + /** * A structure for ipp supported property list. * @@ -221,6 +272,9 @@ enum drm_exynos_planer { * @csc: flag of csc supporting. * @crop: flag of crop supporting. * @scale: flag of scale supporting. + * @blending: flag of blending supporting. + * @dithering: flag of dithering supporting. + * @colorfill: flag of colorfill supporting. * @refresh_min: min hz of refresh. * @refresh_max: max hz of refresh. * @crop_min: crop min resolution. @@ -238,9 +292,11 @@ struct drm_exynos_ipp_prop_list { __u32 csc; __u32 crop; __u32 scale; + __u32 blending; + __u32 dithering; + __u32 colorfill; __u32 refresh_min; __u32 refresh_max; - __u32 reserved; struct drm_exynos_sz crop_min; struct drm_exynos_sz crop_max; struct drm_exynos_sz scale_min; @@ -290,7 +346,9 @@ enum drm_exynos_color_range { * @prop_id: id of property. * @refresh_rate: refresh rate. * @range: dynamic range for csc. - * @pad: just padding to be 64-bit aligned. + * @blending: blending opeation config. + * @dithering: dithering opeation config. + * @color_fill: color fill value. */ struct drm_exynos_ipp_property { struct drm_exynos_ipp_config config[EXYNOS_DRM_OPS_MAX]; @@ -299,7 +357,9 @@ struct drm_exynos_ipp_property { __u32 prop_id; __u32 refresh_rate; __u32 range; - __u32 pad; + __u32 blending; + __u32 dithering; + __u32 color_fill; }; /* definition of buffer */ |