exynos: Add kernel userspace api for v1

Change-Id: Ic2bbde341316924bc3c9bf3af8cd206c6f3f8f6b
Signed-off-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>

drm: ipptest: support ipp dynamic color range

This patch supports dynamic range for color space conversion.
COLOR_RANGE_LIMITED: selects narrow -> Y(16 to 235), Cb/Cr(16 to 240)
COLOR_RANGE_FULL: selects wide -> Y/Cb/Cr(0 to 255), Wide default

Change-Id: I94190ac3f3630904d2461e226d34378ac2b82b9d
Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>

libdrm/exynos: add support for IPP blending, dithering, and colorfill

This patch adds the fields for IPP bleding, dithering, and colorfill.

Change-Id: Ib9cd7c7b22ee9f1017d1db3ae34d39dea342ffec
Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>

ipptest: added M2M to screen on fimc_m2m_set_mode

This patch added for the function outputing the M2M to a screen.
So, you can check for Image Post processing dirver to screen.
Also you can select the degree about (0, 90, 180, 270).

I will briefly explain the process of the function:
 - Memory(YUV422) ---> IPP ---> Memory(RGB888) ---> Screen
   - Create four DMA memory.
   - Draw the image of the YUV422 format on three DMA memories.
   - Rotate the relevant image by using IPP driver.
   - The rotated image is stored in one DMA memory as the RGB888 format.
   - The one DMA memory output screen.

I referred to the modetest code.

Change-Id: I2bf5738d98a457ced274dc8237df8ef108153e61
Signed-off-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>

exynos/drm: sync with v4.1.36 rebased tree for exynos_ipp_prop_list

There is a problem using the IPP_GET_RPOPERTY ioctl because the
structure exynos_ipp_prop_list is not synchronized. Synchronize with
exynos_ipp_prop_list structure of tizen kernel v4.1.36

Refer below commit of tizen kernel:
- Commit id: 60f8b78 (drm/exynos/gsc: Add rotation hardware limits of gscaler)
- https://review.tizen.org/git/?p=platform/kernel/linux-exynos.git;a=commit;h=60f8b78ad8b75c5c3a52f2ad66897da628153eec

Change-Id: Id1989f571c989afb2c73bd4d654f560c3be4067c
Signed-off-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>

1 files changed, 275 insertions, 0 deletions

diff --git a/exynos/exynos_drm.h b/exynos/exynos_drm.h
index bb7ddb61..e889b36f 100644
--- a/exynos/exynos_drm.h
+++ b/exynos/exynos_drm.h
@@ -144,6 +144,255 @@ struct drm_exynos_g2d_exec {
 	__u64					async;
 };
 
+/* definition of operations types */
+enum drm_exynos_ops_id {
+	EXYNOS_DRM_OPS_SRC,
+	EXYNOS_DRM_OPS_DST,
+	EXYNOS_DRM_OPS_MAX,
+};
+
+/* definition of size */
+struct drm_exynos_sz {
+	__u32	hsize;
+	__u32	vsize;
+};
+
+/* definition of position */
+struct drm_exynos_pos {
+	__u32	x;
+	__u32	y;
+	__u32	w;
+	__u32	h;
+};
+
+/* definition of flip */
+enum drm_exynos_flip {
+	EXYNOS_DRM_FLIP_NONE = (0 << 0),
+	EXYNOS_DRM_FLIP_VERTICAL = (1 << 0),
+	EXYNOS_DRM_FLIP_HORIZONTAL = (1 << 1),
+	EXYNOS_DRM_FLIP_BOTH = EXYNOS_DRM_FLIP_VERTICAL |
+			EXYNOS_DRM_FLIP_HORIZONTAL,
+};
+
+/* definition of rotation degree */
+enum drm_exynos_degree {
+	EXYNOS_DRM_DEGREE_0,
+	EXYNOS_DRM_DEGREE_90,
+	EXYNOS_DRM_DEGREE_180,
+	EXYNOS_DRM_DEGREE_270,
+};
+
+/* definition of planar */
+enum drm_exynos_planer {
+	EXYNOS_DRM_PLANAR_Y,
+	EXYNOS_DRM_PLANAR_CB,
+	EXYNOS_DRM_PLANAR_CR,
+	EXYNOS_DRM_PLANAR_MAX,
+};
+
+/* define of blending operation */
+enum drm_exynos_ipp_blending {
+	IPP_BLENDING_NO,
+	/* [0, 0] */
+	IPP_BLENDING_CLR,
+	/* [Sa, Sc] */
+	IPP_BLENDING_SRC,
+	/* [Da, Dc] */
+	IPP_BLENDING_DST,
+	/* [Sa + (1 - Sa)*Da, Rc = Sc + (1 - Sa)*Dc] */
+	IPP_BLENDING_SRC_OVER,
+	/* [Sa + (1 - Sa)*Da, Rc = Dc + (1 - Da)*Sc] */
+	IPP_BLENDING_DST_OVER,
+	/* [Sa * Da, Sc * Da] */
+	IPP_BLENDING_SRC_IN,
+	/* [Sa * Da, Sa * Dc] */
+	IPP_BLENDING_DST_IN,
+	/* [Sa * (1 - Da), Sc * (1 - Da)] */
+	IPP_BLENDING_SRC_OUT,
+	/* [Da * (1 - Sa), Dc * (1 - Sa)] */
+	IPP_BLENDING_DST_OUT,
+	/* [Da, Sc * Da + (1 - Sa) * Dc] */
+	IPP_BLENDING_SRC_ATOP,
+	/* [Sa, Sc * (1 - Da) + Sa * Dc ] */
+	IPP_BLENDING_DST_ATOP,
+	/* [-(Sa * Da), Sc * (1 - Da) + (1 - Sa) * Dc] */
+	IPP_BLENDING_XOR,
+	/* [Sa + Da - Sa*Da, Sc*(1 - Da) + Dc*(1 - Sa) + min(Sc, Dc)] */
+	IPP_BLENDING_DARKEN,
+	/* [Sa + Da - Sa*Da, Sc*(1 - Da) + Dc*(1 - Sa) + max(Sc, Dc)] */
+	IPP_BLENDING_LIGHTEN,
+	/* [Sa * Da, Sc * Dc] */
+	IPP_BLENDING_MULTIPLY,
+	/* [Sa + Da - Sa * Da, Sc + Dc - Sc * Dc] */
+	IPP_BLENDING_SCREEN,
+	/* Saturate(S + D) */
+	IPP_BLENDING_ADD,
+	/* Max */
+	IPP_BLENDING_MAX,
+};
+
+/* define of dithering operation */
+enum drm_exynos_ipp_dithering {
+	IPP_DITHERING_NO,
+	IPP_DITHERING_8BIT,
+	IPP_DITHERING_6BIT,
+	IPP_DITHERING_5BIT,
+	IPP_DITHERING_4BIT,
+	IPP_DITHERING_MAX,
+};
+
+/**
+ * A structure for ipp supported property list.
+ *
+ * @version: version of this structure.
+ * @ipp_id: id of ipp driver.
+ * @count: count of ipp driver.
+ * @writeback: flag of writeback supporting.
+ * @flip: flag of flip supporting.
+ * @degree: flag of degree information.
+ * @csc: flag of csc supporting.
+ * @crop: flag of crop supporting.
+ * @scale: flag of scale supporting.
+ * @refresh_min: min hz of refresh.
+ * @refresh_max: max hz of refresh.
+ * @crop_min: crop min resolution.
+ * @crop_max: crop max resolution.
+ * @scale_min: scale min resolution.
+ * @scale_max: scale max resolution.
+ * @rot_max: rotation max resolution.
+ */
+struct drm_exynos_ipp_prop_list {
+	__u32	version;
+	__u32	ipp_id;
+	__u32	count;
+	__u32	writeback;
+	__u32	flip;
+	__u32	degree;
+	__u32	csc;
+	__u32	crop;
+	__u32	scale;
+	__u32	refresh_min;
+	__u32	refresh_max;
+	__u32	reserved;
+	struct drm_exynos_sz	crop_min;
+	struct drm_exynos_sz	crop_max;
+	struct drm_exynos_sz	scale_min;
+	struct drm_exynos_sz	scale_max;
+	struct drm_exynos_sz	rot_max;
+};
+
+/**
+ * A structure for ipp config.
+ *
+ * @ops_id: property of operation directions.
+ * @flip: property of mirror, flip.
+ * @degree: property of rotation degree.
+ * @fmt: property of image format.
+ * @sz: property of image size.
+ * @pos: property of image position(src-cropped,dst-scaler).
+ */
+struct drm_exynos_ipp_config {
+	enum drm_exynos_ops_id ops_id;
+	enum drm_exynos_flip	flip;
+	enum drm_exynos_degree	degree;
+	__u32	fmt;
+	struct drm_exynos_sz	sz;
+	struct drm_exynos_pos	pos;
+};
+
+/* definition of command */
+enum drm_exynos_ipp_cmd {
+	IPP_CMD_NONE,
+	IPP_CMD_M2M,
+	IPP_CMD_WB,
+	IPP_CMD_OUTPUT,
+	IPP_CMD_MAX,
+};
+
+/* define of M2M command */
+enum drm_exynos_ipp_cmd_m2m {
+	IPP_CMD_M2M_FILE,
+	IPP_CMD_M2M_DISPLAY,
+	IPP_CMD_M2M_NONE,
+};
+
+/* define of color range */
+enum drm_exynos_color_range {
+	COLOR_RANGE_LIMITED,	/* Narrow: Y(16 to 235), Cb/Cr(16 to 240) */
+	COLOR_RANGE_FULL,	/* Wide: Y/Cb/Cr(0 to 255), Wide default */
+};
+
+/**
+ * A structure for ipp property.
+ *
+ * @config: source, destination config.
+ * @cmd: definition of command.
+ * @ipp_id: id of ipp driver.
+ * @prop_id: id of property.
+ * @refresh_rate: refresh rate.
+ * @range: dynamic range for csc.
+ * @blending: blending opeation config.
+ * @dithering: dithering opeation config.
+ * @color_fill: color fill value.
+ */
+struct drm_exynos_ipp_property {
+	struct drm_exynos_ipp_config config[EXYNOS_DRM_OPS_MAX];
+	enum drm_exynos_ipp_cmd	cmd;
+	__u32	ipp_id;
+	__u32	prop_id;
+	__u32	refresh_rate;
+	__u32	range;
+	__u32	blending;
+	__u32	dithering;
+	__u32	color_fill;
+};
+
+/* definition of buffer */
+enum drm_exynos_ipp_buf_type {
+	IPP_BUF_ENQUEUE,
+	IPP_BUF_DEQUEUE,
+};
+
+/**
+ * A structure for ipp buffer operations.
+ *
+ * @ops_id: operation directions.
+ * @buf_type: definition of buffer.
+ * @prop_id: id of property.
+ * @buf_id: id of buffer.
+ * @handle: Y, Cb, Cr each planar handle.
+ * @user_data: user data.
+ */
+struct drm_exynos_ipp_queue_buf {
+	enum drm_exynos_ops_id	ops_id;
+	enum drm_exynos_ipp_buf_type	buf_type;
+	__u32	prop_id;
+	__u32	buf_id;
+	__u32	handle[EXYNOS_DRM_PLANAR_MAX];
+	__u32	reserved;
+	__u64	user_data;
+};
+
+/* definition of control */
+enum drm_exynos_ipp_ctrl {
+	IPP_CTRL_PLAY,
+	IPP_CTRL_STOP,
+	IPP_CTRL_PAUSE,
+	IPP_CTRL_RESUME,
+	IPP_CTRL_MAX,
+};
+
+/**
+ * A structure for ipp start/stop operations.
+ *
+ * @prop_id: id of property.
+ * @ctrl: definition of control.
+ */
+struct drm_exynos_ipp_cmd_ctrl {
+	__u32	prop_id;
+	enum drm_exynos_ipp_ctrl	ctrl;
+};
+
 #define DRM_EXYNOS_GEM_CREATE		0x00
 #define DRM_EXYNOS_GEM_MAP		0x01
 /* Reserved 0x04 ~ 0x05 for exynos specific gem ioctl */
@@ -155,6 +404,12 @@ struct drm_exynos_g2d_exec {
 #define DRM_EXYNOS_G2D_SET_CMDLIST	0x21
 #define DRM_EXYNOS_G2D_EXEC		0x22
 
+/* IPP - Image Post Processing */
+#define DRM_EXYNOS_IPP_GET_PROPERTY	0x30
+#define DRM_EXYNOS_IPP_SET_PROPERTY	0x31
+#define DRM_EXYNOS_IPP_QUEUE_BUF	0x32
+#define DRM_EXYNOS_IPP_CMD_CTRL	0x33
+
 #define DRM_IOCTL_EXYNOS_GEM_CREATE		DRM_IOWR(DRM_COMMAND_BASE + \
 		DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create)
 #define DRM_IOCTL_EXYNOS_GEM_MAP		DRM_IOWR(DRM_COMMAND_BASE + \
@@ -172,8 +427,18 @@ struct drm_exynos_g2d_exec {
 #define DRM_IOCTL_EXYNOS_G2D_EXEC		DRM_IOWR(DRM_COMMAND_BASE + \
 		DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec)
 
+#define DRM_IOCTL_EXYNOS_IPP_GET_PROPERTY	DRM_IOWR(DRM_COMMAND_BASE + \
+		DRM_EXYNOS_IPP_GET_PROPERTY, struct drm_exynos_ipp_prop_list)
+#define DRM_IOCTL_EXYNOS_IPP_SET_PROPERTY	DRM_IOWR(DRM_COMMAND_BASE + \
+		DRM_EXYNOS_IPP_SET_PROPERTY, struct drm_exynos_ipp_property)
+#define DRM_IOCTL_EXYNOS_IPP_QUEUE_BUF	DRM_IOWR(DRM_COMMAND_BASE + \
+		DRM_EXYNOS_IPP_QUEUE_BUF, struct drm_exynos_ipp_queue_buf)
+#define DRM_IOCTL_EXYNOS_IPP_CMD_CTRL		DRM_IOWR(DRM_COMMAND_BASE + \
+		DRM_EXYNOS_IPP_CMD_CTRL, struct drm_exynos_ipp_cmd_ctrl)
+
 /* EXYNOS specific events */
 #define DRM_EXYNOS_G2D_EVENT		0x80000000
+#define DRM_EXYNOS_IPP_EVENT		0x80000001
 
 struct drm_exynos_g2d_event {
 	struct drm_event	base;
@@ -184,4 +449,14 @@ struct drm_exynos_g2d_event {
 	__u32				reserved;
 };
 
+struct drm_exynos_ipp_event {
+	struct drm_event	base;
+	__u64			user_data;
+	__u32			tv_sec;
+	__u32			tv_usec;
+	__u32			prop_id;
+	__u32			reserved;
+	__u32			buf_id[EXYNOS_DRM_OPS_MAX];
+};
+
 #endif