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author | Anas Nashif <anas.nashif@intel.com> | 2012-11-08 06:36:54 -0800 |
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committer | Anas Nashif <anas.nashif@intel.com> | 2012-11-08 06:36:54 -0800 |
commit | cccf3a7c7888ce7bd7a8f8d48a34c5474ad9feeb (patch) | |
tree | 7f31b77ace4359e85dc3d3f66c853858c0bca7a4 /examples/mux.vhdl | |
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Imported Upstream version 1.8.2upstream/1.8.2
Diffstat (limited to 'examples/mux.vhdl')
-rw-r--r-- | examples/mux.vhdl | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/examples/mux.vhdl b/examples/mux.vhdl new file mode 100644 index 0000000..211e56e --- /dev/null +++ b/examples/mux.vhdl @@ -0,0 +1,32 @@ +------------------------------------------------------- +--! @file +--! @brief 2:1 Mux using with-select +------------------------------------------------------- + +--! Use standard library +library ieee; +--! Use logic elements + use ieee.std_logic_1164.all; + +--! Mux entity brief description + +--! Detailed description of this +--! mux design element. +entity mux_using_with is + port ( + din_0 : in std_logic; --! Mux first input + din_1 : in std_logic; --! Mux Second input + sel : in std_logic; --! Select input + mux_out : out std_logic --! Mux output + ); +end entity; + +--! @brief Architure definition of the MUX +--! @details More details about this mux element. +architecture behavior of mux_using_with is +begin + with (sel) select + mux_out <= din_0 when '0', + din_1 when others; +end architecture; + |