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10 days[Tizen] Bypass GBS build fail for exitcode 143 (#637)accepted/tizen/unified/x/asan/20241114.221516accepted/tizen/unified/x/20241114.135527accepted/tizen/unified/20241121.055647tizen_devtizenaccepted/tizen_unified_x_asanaccepted/tizen_unified_xaccepted/tizen_unified이형주/MDE Lab(SR)/삼성전자1-1/+1
2024-11-01[Tizen] Add more coreclr skips for riscv64 (BPI-F3)Gleb Balykov1-0/+1
2024-09-12Sync aug24 release/8.0-tizen (#595)accepted/tizen/unified/x/asan/20241013.235448accepted/tizen/unified/x/20240913.014835accepted/tizen/unified/toolchain/20241004.101213accepted/tizen_unified_toolchainTimur Mustafin/Advanced System SW Lab /SRR/Staff Engineer/Samsung Electronics119-374/+2777
2024-09-08[Tizen] Add more coreclr skips for armel (RPI4)Gleb Balykov2-0/+2
2024-08-07[Tizen] Fix typo in coreclr skips for armel (RPI4) and riscv64 (VisionFive2)Gleb Balykov2-2/+2
2024-08-07Use ConcurrentDictionary in runtimecounters test (#105520)Jan Kotas1-29/+32
2024-07-26For transition profiler callbacks, always load the thread (#105104)Jeremy Koritzinsky5-14/+51
2024-07-17[Tizen] Enable HotReload feature for RISCV64.Mikhail Kurinnoi1-2/+2
2024-07-15[RISC-V] Add RiscV64 arch to tests/JIT/Stress/ABI/ (#103830)t-mustafin2-0/+35
2024-07-15[RISC-V] Add riscv64 arch to tracing/eventpipe/processinfo tests (#103832)Gleb Balykov3-18/+12
2024-07-15[Tizen] Add more coreclr skips for armel (RPI4) and riscv64 (VisionFive2)Gleb Balykov2-0/+4
2024-07-13[Tizen] Microsoft.Diagnostics.Tracing.TraceEvent version up (#548)Timur Mustafin/Advanced System SW Lab /SRR/Staff Engineer/Samsung Electronics21-1/+17327
2024-07-13[Tizen] Add more coreclr skips for armel (RPI4) and riscv64 (VisionFive2)Gleb Balykov2-0/+2
2024-07-09[Tizen] Check if event are already prepared each second (60 seconds max)Gleb Balykov1-9/+11
2024-07-09[Tizen] Fix out_of_range_fp_to_int_conversions testTimur Mustafin1-1/+1
2024-07-05[Tizen] Add more coreclr skips for armel (RPI4) and riscv64 (VisionFive2)Gleb Balykov2-0/+2
2024-07-05[Tizen] Skip Runtime_56953Timur Mustafin2-0/+2
2024-06-10Update thunktemplates.S (#100066) (#529)accepted/tizen/unified/x/asan/20240625.091415accepted/tizen/unified/x/20240610.223834accepted/tizen/unified/toolchain/20240610.173302이형주/MDE Lab(SR)/삼성전자1-1/+1
2024-06-10Support building against clang 18 (#100258) (#528)이형주/MDE Lab(SR)/삼성전자3-1/+5
2024-06-10[Tizen] Fix crossgen2 mic build (#517)최종헌/MDE Lab(SR)/삼성전자1-2/+1
2024-06-07[RISC-V] Add gcinfodumper implementation.Mikhail Kurinnoi1-57/+41
2024-06-07Sync may31 release/8.0-tizen (#510)Timur Mustafin/Advanced System SW Lab /SRR/Staff Engineer/Samsung Electronics48-2813/+2775
2024-06-07[Tizen] Update riscv64 unsupported coreclr tests (#522)Timur Mustafin/Advanced System SW Lab /SRR/Staff Engineer/Samsung Electronics2-0/+3
2024-05-08[Tizen] Further fix corefx testsGleb Balykov13-24/+61
2024-04-25[Tizen] Add more coreclr skips for RPI4 for armelGleb Balykov2-0/+2
2024-04-18[Tizen] Require coreclr-dbgshim (#464)accepted/tizen/unified/x/20240419.130259이형주/MDE Lab(SR)/삼성전자1-0/+1
2024-04-11Restore StubSecretArg from stackTimur Mustafin1-2/+10
2024-04-02[Tizen] Fix crossgen launch setupGleb Balykov1-2/+2
2024-03-25[Tizen] Add coreclr gcstress skips for RPI4 for armelGleb Balykov1-0/+27
2024-03-25[Tizen] Add coreclr skips for RPI4 for armelGleb Balykov1-0/+29
2024-03-25[Tizen] Update coreclr skips for VisionFive2 riscv64Gleb Balykov1-0/+3
2024-03-25[TIZEN] Add unsupportedTests.GCStress.riscv64.txtTimur Mustafin3-0/+49
2024-03-21[RISC-V] Fix hijack (#99809) (#449)Timur Mustafin/Advanced System SW Lab /SRR/Staff Engineer/Samsung Electronics3-22/+26
2024-03-03[Tizen] Add unsupportedTests.riscv64.txtTimur Mustafin1-0/+38
2024-02-22[Tizen] Merging fix ForMismatchedValuesaccepted/tizen/unified/x/20240226.075414accepted/tizen/unified/toolchain/20240311.065939Timur Mustafin1-3/+3
2024-02-22[RISC-V] Test HalfTest: fixed payload preservation testcase for RISC-V (#96888)Denis Paranichev2-117/+184
2024-02-22[RISC-V] Implement replacing safe-point call instructions under GC_STRESS (#9...Tomasz Sowiński2-12/+65
2024-02-22[RISC-V] Test TotalOrderIeee754ComparerTests: Fix NFloat - NaN testcases for ...Denis Paranichev1-2/+34
2024-02-22Call missing genProduceReg in genCodeForCompare (#97805)Tomasz Sowiński1-5/+7
2024-02-22[RISC-V] Use correct registers set for fast tail call when function needs GSC...yurai0071-0/+4
2024-02-22[RISC-V] GCC crosscompile fixes (#97445)Dmitry Kurtaev2-2/+2
2024-02-22[RISCV] Replace arm64 with riscv64 (#96889)monstercat2-5/+5
2024-02-22[RISC-V] Adjust genRangeCheck for handling integer length stored in 64 bit re...yurai0072-1/+11
2024-02-22[RISC-V] Fix bug in label printing in disasm (#96136)Grzegorz Tomasz Czarnecki2-15/+40
2024-02-22[RISC-V] Add branch label names to disasm (#96057)Grzegorz Tomasz Czarnecki4-76/+200
2024-02-08[RISC-V] Put scalar stack args with sign extension (#97662) (#392)accepted/tizen/unified/x/20240214.051929이형주/MDE Lab(SR)/삼성전자1-0/+8
2024-01-12[Tizen] Add method to write coredump of .NET process (#384)accepted/tizen/unified/riscv/20240115.053917accepted/tizen_unified_riscvMateusz Moscicki/System (PLT) /SRPOL/Engineer/Samsung Electronics9-19/+517
2024-01-11[Tizen] Remove unnecessary requires in the specaccepted/tizen/unified/riscv/20240111.091742Woongsuk Cho1-1/+0
2024-01-04[Tizen] Remove not-working workflows (#377)이형주/MDE Lab(SR)/삼성전자2-60/+0
2023-12-26[RISC-V] Fix ProcessWaitingTests.WaitChain and ProcessWaitingTests.WaitAsyncC...yurai0071-2/+13
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