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authorGleb Balykov <g.balykov@samsung.com>2024-10-27 15:23:40 +0300
committerGleb Balykov/Advanced System SW Lab /SRR/Staff Engineer/Samsung Electronics <g.balykov@samsung.com>2024-11-01 16:38:15 +0300
commit92fb3537686485accd828518c8e10b6fb0ce1eb5 (patch)
treebb028402e96c83a89c432f4398d1014687608478
parentddb8e3e11839e56692b8097dc1df7cf5aa54df70 (diff)
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[Tizen] Add more coreclr skips for riscv64 (BPI-F3)
These tests are gcstress incompatible
-rw-r--r--unsupportedGCStressTests.riscv64.txt1
1 files changed, 1 insertions, 0 deletions
diff --git a/unsupportedGCStressTests.riscv64.txt b/unsupportedGCStressTests.riscv64.txt
index f317658bba8..a4c01551834 100644
--- a/unsupportedGCStressTests.riscv64.txt
+++ b/unsupportedGCStressTests.riscv64.txt
@@ -26,6 +26,7 @@ JIT/Methodical/doublearray/dblarray4_cs_r/dblarray4_cs_r.sh
JIT/Methodical/doublearray/dblarray4_cs_ro/dblarray4_cs_ro.sh
JIT/Performance/CodeQuality/Roslyn/CscBench/CscBench.sh
baseservices/exceptions/simple/ParallelCrashWorkerThreads/ParallelCrashWorkerThreads.sh
+profiler/gc/gc/gc.sh
profiler/handles/handles/handles.sh
profiler/multiple/multiple/multiple.sh
profiler/unittest/getappdomainstaticaddress/getappdomainstaticaddress.sh