From 3daac67dfe8744da2c28e1642d425222ef4d1e1b Mon Sep 17 00:00:00 2001 From: Carol Eidt Date: Mon, 6 Nov 2017 15:54:38 -0800 Subject: ARM64: Fix two register selection issues On ARM64 IP0 and IP1 are not in the register selection order, though there are some cases where they must be allocated. See #14607. So we may see them as free when looking for a register to spill. Also, V15 was missing from the selection order (V16 was in the order twice). Fix #14626 --- src/jit/target.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/jit/target.h') diff --git a/src/jit/target.h b/src/jit/target.h index ad36689346..675f057b65 100644 --- a/src/jit/target.h +++ b/src/jit/target.h @@ -1611,7 +1611,7 @@ typedef unsigned short regPairNoSmall; // arm: need 12 bits REG_V28, REG_V29, REG_V30, REG_V31, \ REG_V7, REG_V6, REG_V5, REG_V4, \ REG_V8, REG_V9, REG_V10, REG_V11, \ - REG_V12, REG_V13, REG_V14, REG_V16, \ + REG_V12, REG_V13, REG_V14, REG_V15, \ REG_V3, REG_V2, REG_V1, REG_V0 #define REG_CALLEE_SAVED_ORDER REG_R19,REG_R20,REG_R21,REG_R22,REG_R23,REG_R24,REG_R25,REG_R26,REG_R27,REG_R28 -- cgit v1.2.3