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2018-09-18[Linux/x86] Fix tests in case of 4-byte alignment for 64-bit types (#17829)Konstantin Baladurin3-5/+17
JIT/Directed/RVAInit/nested JIT/Directed/RVAInit/simple JIT/Regression/CLR-x86-JIT/V1.2-Beta1/b103058/b103058
2018-07-31JIT: port extra check to struct of struct of x promotion to relase/2.1Andy Ayers2-0/+284
Port of #19156. Avoid promoting structs that contain struct fields that themselves wrap single simple fields, if those single simple fields are smaller than their enclosing struct. Otherwise we run the risk of losing track of the "extra" bytes in the innner struct. Addresses #19149.
2018-06-27JIT: Fix bug in finally cloning caused by unsound callfinally reorderingAndy Ayers2-0/+90
Port of #18348 to release/2.1 We need to make sure that if we reorder a callfinally during finally cloning that the callfinally is actually the one being targeted by the last block in the try range. Closes #18332. Linked issue has some more detailed notes.
2018-04-21disable DevDiv_255294 in stress modes. (#17618)Sergey Andreenko1-0/+2
2018-04-11Fixed checks for Avx/Avx2.InsertVector128 to check the type of the second argBrian Sullivan2-0/+96
Added test case JIT\HardwareIntrinsics\X86\Regression\GitHub_17435
2018-04-09Disable some tests under GCStress where they take too long to complete (#17437)Koundinya Veluri6-0/+6
* Disable some tests under GCStress where they take too long to complete https://github.com/dotnet/coreclr/issues/15309
2018-04-06Merge pull request #17418 from CarolEidt/Fix590358Carol Eidt2-0/+94
Handle SIMD8/LONG recasts for LCL_FLD
2018-04-04Handle SIMD8/LONG recasts for LCL_FLDCarol Eidt2-0/+94
Lowering needs to insert a `BITCAST` in the case of a `STORE_LCL_FLD` with mismatched `TYP_SIMD8`/`TYP_LONG` operands, just as for `STORE_LCL_VAR`.
2018-03-30Reject struct promotion of parameters when -GS checks are enabledBrian Sullivan2-0/+147
as we could introduce shadow copies of them. Add new test case: GitHub_17329.cs
2018-03-30add reproSergey Andreenko2-0/+214
2018-03-29Fix GCStress failuresFei Peng10-213/+185
2018-03-28Merge pull request #17126 from CarolEidt/Fix545500Carol Eidt3-4/+214
ARM: Fix reg resolution for doubles
2018-03-28Remove tests of unimplemented ISAs (#17286)Fei Peng1-6/+1
2018-03-27Fix comment in test.Carol Eidt1-4/+3
2018-03-27Merge pull request #17233 from fiigii/portvectortestsCarol Eidt6-0/+712
Port VectorReturn test to Vector128/256<T>
2018-03-26Port VectorReturn test to Vector128/256<T>Fei Peng6-0/+712
2018-03-26Merge pull request #15301 from mikedn/cast-unCarol Eidt2-0/+121
Fix inconsistent handling of zero extending casts
2018-03-25Update use of AsBytes in perf tests to use MemoryMarshal.AsBytes. (#17214)Ahson Khan1-1/+1
2018-03-24[RyuJit/ARM] Fix lsra BuildShiftRotate (#17103)Sergey Andreenko2-0/+140
* add repro * delete BuildShiftRotate for arm * fix GT_LSH_HI and GT_RSH_LO * return the special handling for GT_LSH_HI and GT_RSH_LO * fix the header
2018-03-23Merge pull request #17072 from CarolEidt/Fix545505Carol Eidt2-0/+153
ARM: call compRsvdRegCheck later
2018-03-23Merge pull request #17135 from CarolEidt/DevDiv544985Carol Eidt2-0/+221
ARM: correctly unassign constant double
2018-03-22ARM: correctly unassign constant doubleCarol Eidt2-0/+221
When a `RefTypeFixedReg` is encountered for a floating point register, if it is currently holding a double constant, we need to free both halves - but the current register be either half.
2018-03-22ARM: Fix reg resolution for doublesCarol Eidt2-0/+211
1) When an odd float register becomes free, we may need to add the corresponding (even) double register to `targetRegsReady` (this was the bug) 2) When an even float register becomes free, we can't add it to `targetRegsReady` unless it's other half is also free.
2018-03-22fix Set tests on 32-bit platformsFei Peng2-45/+51
2018-03-22Implement SetAllVector256Fei Peng3-0/+306
2018-03-22Implement AVX SetVector256Fei Peng3-0/+323
2018-03-22Add more tests for AVX Insert/Extract intrinsicsFei Peng20-4/+5108
2018-03-20Merge pull request #16955 from fiigii/moreavxCarol Eidt65-0/+12888
Implement more AVX/AVX2 intrinsics
2018-03-20ARM: call compRsvdRegCheck laterCarol Eidt2-0/+153
For RyuJIT backend, the number of locals can change due to decomposition and lowering. So, determine whether to reserve a register for accessing large state displacements just prior to register allocation. This requires ensuring that the stack offset for promoted longs is fixed up, as for promoted reg structs on ARM64. This is all a bit more difficult on LEGACY_BACKEND because the register allocator can change its mind about whether or not it's going to have a frame, so that is left as before.
2018-03-20JIT: remove boxing for interface call to shared generic struct (#17006)Andy Ayers4-0/+122
Improve the jit's ability to optimize a box-interface call sequence to handle cases where the unboxed entry point requires a method table argument. Added two test cases, one from the inspiring issue, and another where the jit is then able to inline the method. Closes #16982.
2018-03-20Add tests for AVX/AVX2 intrinsicsFei65-0/+12888
2018-03-19JIT: tolerate nonzero constant byrefs in impCheckForNullPointer (#17042)Andy Ayers1-1/+0
With the advent of #16966 we may now see constant nonzero byrefs from things like RVA statics. Tolerate these in `impCheckForNullPointer`. Note previously we'd type these as ints/longs and so bail out of `impCheckForNullPointer` after the first check. Closes #17008.
2018-03-19Fixing the x86 ScalarUnOpTest template to no longer write out of boundsTanner Gooding12-770/+279
2018-03-19Regenerating the x86 HWIntrinsic tests to track each vector size separatelyTanner Gooding703-7710/+7714
2018-03-19Updating the x86 HWIntrinsic templates to track each vector size separatelyTanner Gooding20-863/+863
2018-03-19Updating the x86 HWIntrinsic DataTable types to assert the alignment ↵Tanner Gooding10-10/+70
returned is correct
2018-03-19Regenerating the x86 HWIntrinsics tests to no longer have a GC holeTanner Gooding703-1088/+1088
2018-03-19Fixing the x86 HWIntrinsic test templates to not leave a GC holeTanner Gooding19-29/+29
2018-03-16[Arm64] Disable broken tests dependent on #16310Steve MacLean1-0/+4
2018-03-16[Arm64] Enable HW Intrinsic Simd testsSteve MacLean1-68/+0
2018-03-16Add tests for AVX Insert/Extract helper-intrinsicsFei Peng36-0/+10208
2018-03-16Add tests for AVX Insert/ExtractVector128Fei Peng47-0/+13268
2018-03-16Add tests and templates for AVX2 Insert/ExtractFei Peng40-2/+11731
2018-03-15Convert Sse2 tests to template driven version - part 1Jacek Blaszczynski62-1858/+8200
2018-03-15Merge pull request #16813 from CarolEidt/FixDD544983Carol Eidt2-0/+174
Mark operands of dead FIELD_LIST as unused
2018-03-14Merge pull request #16928 from briansull/fix-16892Brian Sullivan2-0/+145
Fix GH Issue 16892 - GC hole due to GT_INDEX_ADDR
2018-03-14Mark operands of dead FIELD_LIST as unusedCarol Eidt2-0/+174
This requires fixing the side-effects check in dead code elimination. Also, fixes gtSetFlags() to be usable from DCE in the non-legacy case.
2018-03-14Fix GH Issue 16892 - GC hole due to GT_INDEX_ADDRBrian Sullivan2-0/+145
Added test case
2018-03-14Merge pull request #16832 from dotnetrt/StoreNonTemporalCarol Eidt3-0/+239
Implement SSE2 StoreNonTemporal HW intrinsic - complete SSE2 ISA
2018-03-14Merge pull request #16797 from dotnetrt/SetAllVector128_ManagedCarol Eidt4-3/+396
Managed implementation of SetAllVector128 SSE2 helper HW intrinsic
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