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In case of evaluation with implicit function call aborted by ```ICorDebugEval::Abort()```, CoreCLR crash with SIGSEGV at line https://github.com/dotnet/runtime/blob/e25517ea27311297c1e3946acb3b4382d5fa7fef/src/coreclr/src/vm/jitinterface.cpp#L14293 since ```m_pJM``` is ```NULL```.
This happens because during ```EECodeInfo::Init()``` call, ```codeAddress``` parameter provide address inside native code region (this address belong to CallDescrWorkerInternal(), libcoreclr.so), but not address inside managed code, so, ```ExecutionManager::FindCodeRange()``` can't find appropriate ```RangeSection```.
During investigation I found, that at line https://github.com/dotnet/runtime/blob/e25517ea27311297c1e3946acb3b4382d5fa7fef/src/coreclr/src/vm/stackwalk.cpp#L2584 current context was not changed properly (we have wrong ```Eip``` register value).
I found, that ```FuncEvalFrame::UpdateRegDisplay()``` code
https://github.com/dotnet/runtime/blob/e25517ea27311297c1e3946acb3b4382d5fa7fef/src/coreclr/src/debug/ee/debugger.inl#L238-L247
don't have x86/Linux support implemented.
I propose changes, that were already made for other ```UpdateRegDisplay()``` implementations in order to provide proper context for x86/Linux.
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This change fixes bug #24164: pull request #11366 adds generation of
commands which use PC-relative addressing. But ArmSingleStepper doesn't
implements support for "ADD Rn, PC" command, so when we try to debug
managed code, generated JIT can't be single stepped correctly.
Detailed changes description:
1) added "ADD Rn, PC" command emulation to ArmSingleStepper;
2) asserts added to JIT code generator, which prevents using of CPU
instructions, which address PC (R15) register with except of only "ADD
Rn, PC" instruction (asserts generated only in Debug builds).
Normally PC register shouldn't be used in arithmetic commands almost in
all cases.
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* Fix hijacking for ARM/ARM64/x86 on Unix
We were not checking the case when we have interrupted a thread inside
of a function epilog for other architectures than amd64. When such an
interruption happens, GS cookie check in a stack walking has failed,
since we are unable to decode GS cookie location when the IP is in
epilog.
This fix implements IsIPInEpilog for all architectures and makes the
check unconditional.
Change-Id: I365be79d6b43ec900084bf2ec031b3555917f8e0
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Change-Id: I0231e9c5209ce39acfe37c54cfcda934b4f773db
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Change-Id: I95043b2fcdccd27e3ae198f7c41d89bde3049c48
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We need to initialize volatileCurrContextPointers because they could be
used by GC in the case of the leaf frame. This patch fixes crashes during
GC when we are single stepping using managed debugger.
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assert to FindOrCreateInitAndAddJitInfo when on arm to ensure the thumb bit is set
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Signed-off-by: Petr Bred <p.bred@samsung.com>
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It can get rid of possible problems with corrupted NI files if crossgen
will be killed during image saving.
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Change-Id: I7937dfffeb7500d37b4e2da485a563a442b38b8c
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coreclr (xmm bug)"
This reverts commit a6695d168396847df8d006a8743c84e5141824af.
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We need to flush instruction cache only for pages that have relocations
instead of full sections because otherwise application's shared clean
memory is increased in some cases on Linux.
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(xmm bug)
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* Separate sections READONLY_VCHUNKS and READONLY_DICTIONARY
* Remove relocations for second-level indirection of Vtable in case FEATURE_NGEN_RELOCS_OPTIMIZATIONS is enabled.
Introduce FEATURE_NGEN_RELOCS_OPTIMIZATIONS, under which NGEN specific relocations optimizations are enabled
* Replace push/pop of R11 in stubs with
- str/ldr of R4 in space reserved in epilog for non-tail calls
- usage of R4 with hybrid-tail calls (same as for EmitShuffleThunk)
* Replace push/pop of R11 for function epilog with usage of LR as helper register right before its restore from stack
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* [x86/Linux] Fix marshalling struct with 64-bit types
The System V ABI for i386 defines 4-byte alignment for 64-bit types.
* [Linux/x86] Fix marshalling tests in the case of System V i386 ABI
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There have been no -pie linker option.
This patch adds -pie linker option into crossgen(for tizen)
This originates from 0024-Add-pie-to-linker-option.patch
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* Sign xstate binary from correct location
* Only submit xstate binary for x86
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This file is only catalog signed in RS4. Sign during the build. To achieve this copy the CRT binaries locally rather than referencing from the UCRT location directly.
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Port of #19156.
Avoid promoting structs that contain struct fields that themselves
wrap single simple fields, if those single simple fields are smaller
than their enclosing struct.
Otherwise we run the risk of losing track of the "extra" bytes in the
innner struct.
Addresses #19149.
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* Skip old time zones with offsets higher than 14h
* apply offline feedback
* fix braces
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The MUSL implementation of sigaltstack checks that the ss.ss_size is
larger or equal than the MINSIGSTKSZ even when the ss_flags is set
to SS_DISABLE even though Linux man page for sigaltstack states that
when this flag is set, all other ss fields are ignored.
We were not setting the ss_size in this case and it was causing a memory
leak for each thread that has terminated on MUSL based Linux distros
like Alpine.
Glibc implementation doesn't check the ss_size when the SS_DISABLE is set
so the problem was really MUSL specific.
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Port of #18348 to release/2.1
We need to make sure that if we reorder a callfinally during finally cloning
that the callfinally is actually the one being targeted by the last block in
the try range.
Closes #18332. Linked issue has some more detailed notes.
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Reimplement most of Array.Clear in managed code using Span Clear helpers.
Fixes dotnet/corefx#29848
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(#18667)
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* Allow ILCodeVersion to fallback to default IL
For compat with profilers that used our APIs in unexpected ways we can allow
the ILCodeVersion to fallback to the default IL code when no IL was explicitly
given.
* Fix incorrect usage of ILCodeVersion::AsNode (issue #18602)
When the debugger is querying the active rejit IL for an IL method that has not been rejitted it incorrectly creates a VMPTR_ILCodeVersionNode for a code version that shouldn't have one.
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Fixes #30263
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(#18505) (#18526)
macOS 10.12+ supports clock_gettime (HAVE_CLOCK_MONOTONIC is defined)
However, mach_absolute_time has better resolution and should be used
as the primary clock source.
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For some reason, the Alpine docker container running on a SELinux host maps
heap as RWX. When we allocate alternate stack from the heap, we also
change the protection of the first page to PROT_NONE so that it can
serve as a guard page to catch stack overflow. And when we free the
alternate stack, we restore the protection back to PROT_READ |
PROT_WRITE. The restoration fails in Alpine docker container running on
a SELinux host with EPROT failure and the SELinux log reports that an
attempt to change heap to executable was made. So it looks like the
kernel has added the PERM_EXEC to the permissions we have passed to the
mprotect call. There is a code in the mprotect implementation that can
do that, although I don't fully understand the conditions under which it
happens. This is driven by the VM_MAYEXEC flag in the internal VMA block
structure.
To fix that, I've modified the alternate stack allocation to use mmap /
munmap instead of C heap allocation.
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StompWriteBarrier(WriteBarrierOp::StompResize) on ARM (#18107)
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in PAL and GC on ARM and ARM64
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For ARM, doing a secure delegate call requires adding
a custom calling convention argument R4 as the address of the
secure delegate invoke indirection cell. This is done using the
fgMorphArgs nonStandardArgs mechanism, and the argument is added
at the end. For calls with 4 or more register arguments, this
didn't work: we would initially set the non-standard arg as a
non-register argument, and the nonStandardArgs check didn't
consider converting an argument from a stack argument back to
a register argument. The fix allows nonStandardArgs to be either
stack or register arguments, no matter what their place in the
argument list would imply.
Fixes #17738
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