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AgeCommit message (Expand)AuthorFilesLines
2017-06-09Merge pull request #12200 from erozenfeld/FastTailCallLoweringFixEugene Rozenfeld1-5/+5
2017-06-09Merge pull request #12184 from rartemev/legacy_jit_1Roman Artemev6-15/+82
2017-06-09Fix fast tail call lowering bug.Eugene Rozenfeld1-5/+5
2017-06-09Merge pull request #12189 from mskvortsov/FixExplicitContainednessCarol Eidt1-3/+11
2017-06-09Merge pull request #10996 from mikedn/magic-udivPat Gavlin6-109/+551
2017-06-09RyuJIT/ARM32: Fix failures related to explicit containednessMikhail Skvortcov1-3/+11
2017-06-09delete DECLARE_TYPED_ENUM (#12177)Sergey Andreenko9-143/+118
2017-06-08Enable legacy jit for x86Roman Artemev6-15/+82
2017-06-08Merge pull request #11901 from CarolEidt/RegValCarol Eidt22-455/+501
2017-06-08Merge pull request #12172 from pgavlin/gh12154Pat Gavlin1-1/+1
2017-06-08Merge pull request #12148 from mikedn/oper-dumpRussell C Hadley14-212/+195
2017-06-08Don't dump an uninitialized bitset in LSRA.Pat Gavlin1-1/+1
2017-06-08Merge pull request #12005 from wateret/wip-armel-lsraCarol Eidt4-6/+43
2017-06-07Merge pull request #12155 from pgavlin/LclVarChecksPat Gavlin2-0/+55
2017-06-07Format code.Pat Gavlin1-1/+1
2017-06-08[RyuJIT/armel] Support putting floating-point argsHanjoung Lee4-6/+43
2017-06-07Address PR feedback.Pat Gavlin2-10/+23
2017-06-07Merge pull request #12142 from BruceForstall/ReduceNowayBruce Forstall6-40/+39
2017-06-07Merge pull request #12087 from sdmaclea/PR-JIT-AcquireRelease-SimpleCasesCarol Eidt4-20/+91
2017-06-07Add lclVar semantic checks to CheckLIR.Pat Gavlin1-0/+42
2017-06-07delete BLOCKSET_INIT_NOCOPY and BLOCKSET_INIT. (#12144)Sergey Andreenko4-20/+12
2017-06-07rename temp variables with meaningful names. (#12023)Sergey Andreenko1-26/+22
2017-06-07Simplify genRegArgNext() (#12124)Bruce Forstall1-38/+22
2017-06-08Make JIT dumps more readableMike Danes14-212/+195
2017-06-07Merge pull request #12138 from pgavlin/CheckLIRCodegenPat Gavlin1-0/+2
2017-06-07Convert some very common noway_assert to simple assertBruce Forstall6-40/+39
2017-06-07Run the LIR checker before codegen.Pat Gavlin1-0/+2
2017-06-07Merge pull request #12122 from BruceForstall/CleanupEffectiveValBruce Forstall6-13/+13
2017-06-07Disable signed magic division in minopts modeMike Danes1-0/+5
2017-06-07Add signed magic division tablesMike Danes1-1/+61
2017-06-07Move GetSignedMagicNumberForDivide to utils.cppMike Danes3-87/+103
2017-06-07Do unsigned magic divisionMike Danes6-32/+393
2017-06-07Make containedness explicitCarol Eidt22-455/+501
2017-06-06More formattingCarol Eidt1-2/+2
2017-06-06FormattingCarol Eidt1-6/+6
2017-06-06Streamline LSRA for non-enregistered lclVarsCarol Eidt4-489/+710
2017-06-06Remove use of gtEffectiveVal in RyuJIT codegenBruce Forstall6-13/+13
2017-06-06Merge pull request #12079 from hseok-oh/ryujit/fix_11850Bruce Forstall1-1/+1
2017-06-06Fix for CoreRT issue https://github.com/dotnet/corert/issues/3672 (armel tize...sergey ignatov1-7/+15
2017-06-06new JitEE interface method: expandRawHandleIntrinsic (#12071)Sergey Andreenko3-21/+60
2017-06-06Fix crash due to lack of PSPSym in the CoreRT ABI (#12082)Petr Bred1-5/+6
2017-06-05Merge pull request #11205 from mskvortsov/FixFloatingLdStBrian Sullivan10-241/+240
2017-06-05Merge pull request #11884 from mikedn/arm-cmp-setccPat Gavlin8-232/+90
2017-06-05Do not set GTF_IND_UNALIGNED on byte sized typesSteve MacLean, Qualcomm Datacenter Technologies, Inc1-4/+4
2017-06-05[Arm64] Respond to review commentsSteve MacLean, Qualcomm Datacenter Technologies, Inc2-5/+9
2017-06-05[Arm64] Handle exclusive decode group in insEncodeDatasizeLS()Steve MacLean, Qualcomm Datacenter Technologies, Inc1-1/+3
2017-06-05[Arm64] Use Store Release when practical for genCodeForStoreIndSteve MacLean, Qualcomm Datacenter Technologies, Inc1-7/+36
2017-06-05[Arm64] Use Load Acquire when practical for genCodeForIndirSteve MacLean1-8/+44
2017-06-05More ldar/stlr supportSteve MacLean, Qualcomm Datacenter Technologies, Inc1-0/+6
2017-06-05[Arm64] Add emitInsTargetRegSize support for ldar/stlrSteve MacLean, Qualcomm Datacenter Technologies, Inc1-0/+6
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