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targets.
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Fix GT_LOCKADD register specification.
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Use field type value-numbering local field stores
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Method `VNPairApplySelectorsAssign` takes the type of the value being
assigned, so when processing a store to a field of a local struct, pass
the type of the field rather than the type of the local; failure to do so
was blocking propagation of the value number to subsequent loads of the
same field due to the type mismatch.
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Widen basic block flag field to 64 bits
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Ifdef more unused code that uses ReadProcessMemory. Move the current
memory probing in the transport to PAL_ProbeMemory. Add PAL_ProbeMemory
to dac PAL exports.
PAL_ProbeMemory may be changed to use write/read on a pipe to
validate the memory as soon as we make it perform as well as
the current code.
Remove ReadProcessMemory tests and add PAL_ProbeMemory pal tests.
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Flag field is currently full, and I need at least one more bit to identify
the start of a cloned finally.
Widen to 64 bits and update a few uses. Also removed an unused copy.
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Correctly sequence fgMorphModToSubMulDiv
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Streamline LSRA resolution
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Fix SIMD Scalar Move Encoding: VEX.L should be 0
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For SIMD Scalar Move instructions such as vmovlpd, vmovlps, vmovhps,
vmovhps and vmovss on AVX system, JIT should ensure that those
instructions are encoded with VEX.L=0, because encoding them with
VEX.L=1 may encounter unpredictable behavior across different
processor generations. The reason of VEX.L is encoded with 1 is
because JIT calls compiler->getSIMDVectorType() which returns
EA_32BYTE, and it is been passed into emitter AddVexPrefix() which
ends up encoded VEX.L=1, the fix is to pass target type and base
type for those instructions to ensure that VEX.L=0 at emitter
AddVexPrefix()
Fix #8328
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This method was creating a temp, but the final result was a GT_SUB with
a use of the temp as its op1, and it was not setting GTF_REVERSE_OPS.
This led to a liveness assert in LSRA.
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LclVar ref counts must be incremented before attempting to remove the
morphed statement, since doing so decrements ref counts (and thus
requires refcounts to be conservatively correct).
Fixes VSO 359734.
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Fix consume-order checking in codegen.
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The codegen for the non-readytorun path (used on CoreCLR) requires the
runtime to support general purpose virtual method resolution based on a
method handle. CoreRT doesn't have such helpers.
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Ryujit/ARM32 Initial Lowering::IsContainableImmed for ARM
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The switch to LIR invalidated the correspondence between a node's
sequence number and the order in which it must be consumed with respect
to other nodes. This in turn made the consume-order checks during code
generation incorrect.
This change introduces a new field, `gtUseNum`, that is used during code
generation to check the order in which nodes are consumed. Re-enabling
these checks revealed a bug in code generation for locked instructions
on x86, which were consuming their operands out-of-order; this change
also contains a fix for that bug.
Fixes #7963.
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TreeNodeInfoInitCmp attempts to eliminate the cast from
`cmp(cast<ubyte>(x), icon)` by narrowing the compare to ubyte. This should
only happen if the constant fits in a byte so it can be narrowed too,
otherwise codegen produces an int sized compare. (or a byte sized compare
with a truncated constant if we try to use GTF_RELOP_SMALL).
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Initial implementation of IsContainableImmed for ARM.
Signed-off-by: Hyung-Kyu Choi <hk0110.choi@samsung.com>
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Ryujit/ARM32: Implement Lowering::LowerCast for ARM
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Simple integer to interger type conversion is passed.
Add comment for LowreCast with C++ comment style.
Signed-off-by: Hyung-Kyu Choi <hk0110.choi@samsung.com>
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Fix to issue 8286.
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Fix missing flags on GT_DYN_BLK node
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Last 4K or so lines of flowgraph.cpp were not being formatted because
the clang-format on directive had a typo.
Fix the typo and reformat the latter part of the file.
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Fix to issue 8287.
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Fix unix unwind info
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Disable special put args for LIMIT_CALLER on x86.
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Correct an assertion in LSRA.
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Windows uses offset from stack pointer, when unix has to use offset from
caninical frame address,
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* Remove sscanf
* Remove sprintf
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`verifyFinalAllocation` asserts that if a non-BB interval RefPosition
that is either spilled or is the interval's last use does not have a
register, then that ref position must be marked `AllocateIfProfitable`.
However, this situation can also arise in at least one other situation:
an unused parameter will have at least one ref position that may not be
allocated to a register. This change corrects the assertion to check
`RefPosition::RequiresRegister` rather than
`RefPosition::AllocateIfProfitable`.
Fixes VSO 299207.
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that we create.
We typically don't have any information about the address supplied to a GT_DYN_BLK so we should
conservatively allow that it can either be a null pointer or could point into the GC heap.
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On x86, `LSRA_LIMIT_CALLER` is too restrictive to allow the use of special
put args: this stress mode leaves only three registers allocatable--eax,
ecx, and edx--of which the latter two are also used for the first two
integral arguments to a call. This can leave us with too few registers to
succesfully allocate in situations like the following:
t1026 = lclVar ref V52 tmp35 u:3 REG NA <l:$3a1, c:$98d>
/--* t1026 ref
t1352 = * putarg_reg ref REG NA
t342 = lclVar int V14 loc6 u:4 REG NA $50c
t343 = const int 1 REG NA $41
/--* t342 int
+--* t343 int
t344 = * + int REG NA $495
t345 = lclVar int V04 arg4 u:2 REG NA $100
/--* t344 int
+--* t345 int
t346 = * % int REG NA $496
/--* t346 int
t1353 = * putarg_reg int REG NA
t1354 = lclVar ref V52 tmp35 (last use) REG NA
/--* t1354 ref
t1355 = * lea(b+0) byref REG NA
Here, the first `putarg_reg` would normally be considered a special put arg,
which would remove `ecx` from the set of allocatable registers, leaving
only `eax` and `edx`. The allocator will then fail to allocate a register
for the def of `t345` if arg4 is not a register candidate: the corresponding
ref position will be constrained to { `ecx`, `ebx`, `esi`, `edi` }, which
`LSRA_LIMIT_CALLER` will further constrain to `ecx`, which will not be
available due to the special put arg.
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In lowerxarch.cpp, local variable srcUns is defined but not used
at Lowering::LowerCast(GenTree* tree).
Signed-off-by: Hyung-Kyu Choi <hk0110.choi@samsung.com>
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Merge changes from TFS
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Use a left-leaning comma tree when morphing a stelem.ref helper.
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[tfs-changeset: 1640669]
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Use only lower floats for Vector3 dot and equality
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Fix to issue 8356.
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fgMorphCall may change a call to the stelem.ref helper that is storing a
null value into a simple store. This transformation needs to construct a
comma tree to hold the argument setup nodes present on the call if any
exist. Originally this tree was constructed in right-leaning fashion
(i.e. the first comma node was the root of the tree and each successive
comma node was the RHS of its parent). Unfortunately, this construction
did not automatically propagate the flags of a comma node's children to
the comma node, since not all of each comma node's actual children were
available at the time it was constructed. Constructing the tree in
left-leaning fashion (i.e. the first comma node is the left-most child
and the final comma node is the root of the tree) allows the flag
propagation to be performed correctly by constrution.
Fixes VSO 297215.
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Remove a use of `gtGetOp` in earlyprop.
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Instead, use `GenTreeIndir::Addr`, as some indirections are not simple
operators.
Fixes VSO 289704.
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For both dot product and comparisons that produce a boolean result, we need to use only the lower 3 floats. The bug was exposed by a case where the result of a call was being used in one of these operations without being stored to a local (which would have caused the upper bits to be cleared).
Fix #8220
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Only do resolution when required, and only for variables that may need it.
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