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path: root/src/jit/simdcodegenxarch.cpp
AgeCommit message (Expand)AuthorFilesLines
2019-05-30Fixes for building the Desktop JIT in CodegenMirrorBrian Sullivan1-0/+1
2019-05-17Ensure we don't underestimate the code size for 4 byte SSE instruction. (#24555)Tanner Gooding1-26/+44
2019-04-22Fix Arm64 UpperVector save/restore (#24043)Carol Eidt1-2/+1
2019-04-12Don't Free UpperVector (#23889)Carol Eidt1-2/+2
2019-04-04Improve Upper Vector Save/Restore (#23344)Carol Eidt1-18/+31
2019-03-28Delete simple unused vars2 (#23491)Sergey Andreenko1-1/+0
2019-03-27Revert "Delete unused variables in jit. Part 2. (#23481)" (#23488)Sergey Andreenko1-0/+1
2019-03-27Delete unused variables in jit. Part 2. (#23481)Sergey Andreenko1-1/+0
2019-01-22Fix SIMD12 GT_STORE_LCL_FLDBruce Forstall1-1/+1
2018-11-29Updating genSIMDZero to only use `xorps` (#21249)Tanner Gooding1-3/+5
2018-06-29Corrected a few typos in the documentation and comments (#18706)Phil Garcia1-1/+1
2018-05-24Typo (#18122)John Doe1-1/+1
2018-05-22Remove JIT LEGACY_BACKEND code (#18064)Bruce Forstall1-5/+2
2018-01-31Delete GenTreePtr. (#16027)Sergey Andreenko1-4/+4
2018-01-24Disable the ConvertToUInt intrinsics by removing them from simdintrinsiclist.hCarol Eidt1-6/+2
2018-01-24Disable FP to Unsigned Vector ConversionsCarol Eidt1-2/+0
2017-12-13get rid of TYP_CHARFei Peng1-12/+10
2017-11-15Fix #15035Fei Peng1-8/+26
2017-11-14Change VEX-encoding selection to avoid AVX-SSE transition penaltiesFei Peng1-82/+38
2017-10-25Decoupling SIMD levels from instruction setsFei Peng1-64/+64
2017-10-03remove FEATURE_AVX_SUPPORT flagFei Peng1-6/+0
2017-10-02Simplify SIMD EQ/NE optimizationMike Danes1-39/+6
2017-09-27fix bad VEX.vvvv to avoid false register dependencyFei Peng1-2/+2
2017-05-25Make untracked lclVars containedCarol Eidt1-5/+7
2017-05-10add jit intrinsic support for vector conversion/narrow/widen on AMD64 and x86...helloguo1-14/+847
2017-04-14Introduce API for codegen getting temp registers from gtRsvdRegsBruce Forstall1-56/+22
2017-02-13Directly support Min/Max intrinsic for Vector<T> on SSE3_4 and above targetsFei Peng1-0/+38
2017-02-05Enable SIMD for RyuJIT/x86Bruce Forstall1-25/+114
2016-12-21Use Pabsd/pabsw/pabsb instructions for Abs SIMD intrinsic on SSE4 and above t...sivarv1-1/+21
2016-12-15Merge pull request #8329 from litian2025/Fix_SIMDScalarMoveEncodingSivarv1-16/+17
2016-12-14Fix SIMD Scalar Move Encoding: VEX.L should be 0Li Tian1-16/+17
2016-12-07Use only lower floats for Vector3 dot and equalityCarol Eidt1-11/+47
2016-12-02RyuJIT/x86: Implement TYP_SIMD12 supportBruce Forstall1-7/+55
2016-11-28Enable using SSE3_4 instruction set for SIMD codegen.sivarv1-56/+107
2016-11-23Change vector equality to use pmovmskbMike Danes1-60/+17
2016-10-27Initial RyuJIT x86 SIMD supportBruce Forstall1-2/+2
2016-10-27Introduce new CORJIT_FLAGS typeBruce Forstall1-1/+1
2016-10-21Optimize Vector<int>.Dot on AVX.sivarv1-71/+131
2016-09-29Merge pull request #7407 from sivarv/simdOptSivarv1-26/+49
2016-09-29Optimize codegen when SIMD (in)Equality that produces bool result is compared...sivarv1-26/+49
2016-09-28Fix lowering's containment analysis.Pat Gavlin1-0/+1
2016-09-27Optimize SIMD codegen for (in)equality check against zero that produces bool ...sivarv1-82/+95
2016-09-23Optimize codegen for SIMDIntrinsicGetItem when SIMD vector is a memory-op.sivarv1-0/+53
2016-09-21Support Lower to reserve internal register(s) different from targetReg.sivarv1-56/+8
2016-08-11Reformat jit sources with clang-tidy and formatMichelle McDaniel1-361/+344
2016-07-29Massage code for clang-formatMichelle McDaniel1-5/+7
2016-07-07Fix RyuJIT/x86 fgMorphMultiregStructArg NYIBruce Forstall1-2/+2
2016-06-07Methods to check for integer constants and zeroCarol Eidt1-4/+3
2016-03-251stClassStructs: Replace GT_LDOBJ with GT_OBJCarol Eidt1-8/+12
2016-02-19Fix for SIMD intrinsic Initialize expansion.Eugene Rozenfeld1-28/+67
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