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path: root/src/jit/lsra.cpp
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2018-03-28Merge pull request #17126 from CarolEidt/Fix545500Carol Eidt1-3/+44
2018-03-27Fix commentCarol Eidt1-1/+3
2018-03-26Fix conditionCarol Eidt1-2/+16
2018-03-23Merge pull request #17072 from CarolEidt/Fix545505Carol Eidt1-17/+36
2018-03-22ARM: correctly unassign constant doubleCarol Eidt1-4/+2
2018-03-22ARM: Fix reg resolution for doublesCarol Eidt1-3/+28
2018-03-21Fix release buildCarol Eidt1-1/+1
2018-03-21Remove REG_OPT_RSVD from LSRA's candidate masks if it's reserved.Carol Eidt1-16/+24
2018-03-20ARM: call compRsvdRegCheck laterCarol Eidt1-1/+12
2018-03-09Fix LSRA enregisterLocalVarsCarol Eidt1-1/+15
2018-02-22Handle a restored double Interval at block boundaryCarol Eidt1-0/+6
2018-02-18Merge pull request #16422 from CarolEidt/Fix15037Carol Eidt1-5/+12
2018-02-16Don't set delayRegFree if no targetCarol Eidt1-5/+12
2018-02-16Correctly handle check for busy double regCarol Eidt1-15/+33
2018-02-02Consider specialPutArgs for jitStressRegsCarol Eidt1-2/+3
2018-02-01Refactor RefPosition and Interval BuildingCarol Eidt1-2686/+2
2018-01-31Delete GenTreePtr. (#16027)Sergey Andreenko1-27/+27
2018-01-29JIT: don't overlook strong nearby preference in LSRA (#16028)Andy Ayers1-2/+2
2018-01-23Adjust minRegs for SELECT stress modesCarol Eidt1-40/+62
2018-01-10Fix ARM GCStress hole with byref write barrier helperBruce Forstall1-4/+42
2018-01-05Refactor minRegCount and eliminate autoCarol Eidt1-120/+98
2017-12-20LSRA: Replace operandToLocationInfoMap with a listCarol Eidt1-15/+9
2017-12-19Fix for armel double passed as longCarol Eidt1-1/+1
2017-12-18Eliminate gtLsraInfo from GenTreeCarol Eidt1-580/+402
2017-12-08Fix typo `_TARGET_ARM` to `_TARGET_ARM_`. This happens mostly in comments exc...Egor Chesakov1-1/+1
2017-11-22[Arm64] Allow IsContainableMemoryOp() useSteve MacLean1-2/+0
2017-11-20Set reg conflicts on contained INDCarol Eidt1-2/+3
2017-11-10[ARM64] SIMD Partial Callee Save SIMD12Steve MacLean1-9/+11
2017-11-07Merge pull request #14853 from sdmaclea/PR-ARM64-SIMD-applyCalleeSaveHeuristicsCarol Eidt1-1/+1
2017-11-07[Arm64] SIMD applyCalleeSaveHeuristicsSteve MacLean1-1/+1
2017-11-06ARM64: Fix two register selection issuesCarol Eidt1-2/+9
2017-11-06Merge pull request #14506 from mikedn/alloc-messBrian Sullivan1-1/+1
2017-11-06Merge pull request #14840 from CarolEidt/ShrinkLSRADumpCarol Eidt1-400/+172
2017-11-03FormattingCarol Eidt1-1/+1
2017-11-03Unassign both floats if assigning doubleCarol Eidt1-6/+50
2017-11-03LSRA Dump: don't print unused regsCarol Eidt1-400/+172
2017-11-02Fix copyOrMoveRegInUseCarol Eidt1-6/+20
2017-10-31PR feedback & fix an error in `isRegInUse`Carol Eidt1-6/+7
2017-10-31Fix checking for reg in useCarol Eidt1-115/+51
2017-10-31Merge pull request #14614 from hqueue/arm/ryujit/issue_14374_pr2Carol Eidt1-15/+113
2017-10-31[RyuJIT/ARM32] Fix resolving TYP_DOUBLE and TYP_FLOAT intervalsHyung-Kyu Choi1-15/+113
2017-10-30Merge pull request #14677 from CarolEidt/Fix14626Carol Eidt1-1/+2
2017-10-29Formatting & typoCarol Eidt1-4/+4
2017-10-27Fix another overly agressive assertCarol Eidt1-25/+33
2017-10-26Fix FixedReg assertCarol Eidt1-4/+7
2017-10-25Avoid allocating IP0 and IP1Carol Eidt1-1/+2
2017-10-25Merge pull request #14588 from hqueue/arm/ryujit/issue_14374_pr1Carol Eidt1-3/+26
2017-10-25[RyuJIT/ARM32] Fix to find a free temp double register correctlyHyung-Kyu Choi1-3/+26
2017-10-24delete unused local variables from jit sources (#14679)Sergey Andreenko1-2/+0
2017-10-23Report registers as dead in GCInfo before the RhpPInvoke helper. (#14664)Sergey Andreenko1-30/+1
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