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path: root/src/jit/lsra.cpp
AgeCommit message (Expand)AuthorFilesLines
2017-10-06Fix RyuJIT/arm32 assertsBruce Forstall1-13/+6
2017-10-05[RyuJIT/armel] Fix regressionHanjoung Lee1-0/+6
2017-10-03Merge pull request #14027 from mikedn/simd-eq-optCarol Eidt1-1/+1
2017-10-02Merge pull request #14220 from wateret/ryu-arm-bitcast-cleanupBruce Forstall1-9/+6
2017-10-02Simplify SIMD EQ/NE optimizationMike Danes1-1/+1
2017-09-28Fixed differenece between produced code in CHK and REL modesRoman Artemev1-1/+1
2017-09-27Merge pull request #14192 from sdmaclea/PR-ARM64-JCMPBrian Sullivan1-1/+30
2017-09-28[RyuJIT/arm32] Code cleanupHanjoung Lee1-9/+6
2017-09-27[Arm64] Fix JCMP lsra bindingSteve MacLean1-1/+15
2017-09-26Fix for a special CoreRT helper CORINFO_HELP_JIT_PINVOKE_BEGIN (#14147)Sergey Andreenko1-1/+30
2017-09-26[Arm64] Fix GT_JCMP lsraSteve MacLean1-0/+15
2017-09-26[Arm64] Add GT_JCMP nodeSteve MacLean1-1/+1
2017-09-26Merge pull request #14171 from wateret/ryu-arm-putarg-bitcastCarol Eidt1-14/+6
2017-09-26[RyuJIT/armarch] Put arguments with GT_BITCASTHanjoung Lee1-14/+6
2017-09-25Merge pull request #14080 from hqueue/arm/ryujit/issue_13750Carol Eidt1-0/+15
2017-09-25[RyuJIT/ARM32] Fix assertion condition in LSRA for ARM32Hyung-Kyu Choi1-0/+15
2017-09-18Sane spill weightsCarol Eidt1-6/+20
2017-09-12Merge pull request #13715 from CarolEidt/LsraInfoInLsraCarol Eidt1-7/+55
2017-09-06Fix VSO 487701 and 487702.Pat Gavlin1-5/+5
2017-09-01Add an assert to getRegisterRecord() that regNum is legalBruce Forstall1-0/+1
2017-08-31[RyuJIT/ARM32] Correct handling of double registers in registerIsAvailable()Alexander Soldatov1-2/+1
2017-08-31[RyuJIT/armel] Fix MultiRegOp definitionHanjoung Lee1-1/+1
2017-08-30Do TreeNodeInfoInit in buildIntervalsCarol Eidt1-7/+55
2017-08-27Merge pull request #13597 from CarolEidt/InfoLinearScanCarol Eidt1-4/+76
2017-08-25Move TreeNodeInfoInit to LinearScanCarol Eidt1-4/+76
2017-08-25Arm Containment CleanupCarol Eidt1-0/+9
2017-08-21Change the position of unassignPhysReg()sjsujinkim1-1/+1
2017-08-18Remove unnecessary genIsValidDoubleReg() assertionsjsujinkim1-13/+7
2017-08-17Merge pull request #13198 from CarolEidt/LowerContainCarol Eidt1-1/+5
2017-08-16Move Containment Analysis to LoweringCarol Eidt1-1/+5
2017-08-16Fix formattingsjsujinkim1-1/+1
2017-08-16Fix genIsValidDoubleReg not foundsjsujinkim1-1/+3
2017-08-16[RyuJIT/ARM32] Add additional unassignToInterval if the currentInterval is TY...sjsujinkim1-14/+129
2017-08-14Merge pull request #13364 from hqueue/arm/ryujit/issue_13363_regression_of_13190Bruce Forstall1-0/+5
2017-08-14[RyuJIT/ARM32] Fix regressionHyung-Kyu Choi1-0/+5
2017-08-11Merge pull request #13332 from wateret/fix-ryuarm-hfaBruce Forstall1-12/+2
2017-08-11[RyuJIT/armel] Fix PutArgReg BuildRefPositionsHanjoung Lee1-12/+2
2017-08-10Merge pull request #13307 from wateret/cleanup-armel-lsracondBruce Forstall1-1/+1
2017-08-10[RyuJIT/armel] Cleanup with OperIsMultiRegOp()Hanjoung Lee1-1/+1
2017-08-08[ARM32/RyuJIT] Set the source candidates for PutArgSplit nodesJiyoung Yun1-0/+14
2017-08-08[ARM32/RyuJIT] Use regtype instead of node's type in PUTARG_SPLIT caseJiyoung Yun1-5/+6
2017-08-07[RyuJIT/armel] Fix ifdef condition and Formatting ErrorHanjoung Lee1-3/+3
2017-08-07[RyuJIT/armel] arg regs are always TYP_INTHanjoung Lee1-7/+9
2017-08-07[RyuJIT/armel] Allocate one more temp for call addressHanjoung Lee1-0/+7
2017-08-07[RyuJIT/armel] Each reg gets own SpillFlag for MultiRegOpHanjoung Lee1-1/+6
2017-08-07[RyuJIT/armel] Make RefPosition arg regs fixedHanjoung Lee1-0/+9
2017-08-03Apply review feedbackHyung-Kyu Choi1-1/+9
2017-08-02[RyuJIT/ARM32] Update allocateBusyReg() with a helper for ARM32Hyung-Kyu Choi1-22/+46
2017-08-02[RyuJIT/ARM32] Unassign a double register properly in allocateBusyReg()Hyung-Kyu Choi1-47/+50
2017-08-02[RyuJIT/ARM32] Update allocateBusy() to test spill candiates with new helpersHyung-Kyu Choi1-116/+48
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