platform/upstream/coreclr - Domain: Dotnet / Core; Licenses: MIT;

Age	Commit message (Collapse)	Author	Files	Lines
2016-07-26	Enable multireg returns on Arm64	Brian Sullivan	1	-4/+4
	Added method IsMultiRegPassedType and updated IsMultiRegReturnType Switched these methods to using getArgTypeForStruct and getReturnTypeForStruct Removed IsRegisterPassable and used IsMultiRegReturned instead. Converted lvIsMultiregStruct to use getArgTypeForStruct Renamed varDsc->lvIsMultiregStruct() to compiler->lvaIsMultiregStruct(varDsc) Skip calling getPrimitiveTypeForStruct when we have a struct larger than 8 bytes Refactored ReturnTypeDesc::InitializeReturnType Fixed missing SPK_ByReference case in InitializeReturnType Fixes for RyiJIt x86 TYP_LONG return types and additional ARM64 work for full multireg support Added ARM64 guard the uses of MAX_RET_MULTIREG_BYTES with FEATURE_MULTIREG_RET Fixes for multireg returns in Arm64 Codegen Added dumping of lvIsMultiRegArg and lvIsMultiRegRet in the assembly output Added check and set of compFloatingPointUsed to InitializeStructReturnType Fixes to handle JIT helper calls that say they return a TYP_STRUCT with no class handle available Placed all of the second GC return reg under MULTIREG_HAS_SECOND_GC_RET ifdefs Added the Arm64 VM changes from Rahul's PR 5175 Update getArgTypeForStruct for x86/arm32 so that it returns TYP_STRUCT for all pass by value cases Fixes for the passing of 3,5,6 or 7 byte sized structs Fix issue on ARM64 where we would back fill into x7 after passing a 16-byte struct on the stack Implemented register shuffling for multi reg Call returns on Arm64 Fixed regression on Arm32 for struct args that are not multi regs Updated Tests.Lst with 23 additional passing tests Changes from codereview feedback
2016-04-22	Fix #3561: assert on RyuJIT x86 when generating shl by 1	Bruce Forstall	1	-2/+2
	This assert hit in the encoder when we were trying to generate an INS_shl_N with a constant of 1, instead of using the special xarch INS_shl_1 encoding, which saves a byte. It turns out, the assert was and in fact amd64 does generate the suboptimal encoding currently. The bad code occurs in the RMW case of genCodeForShift(). It turns out that function is unnecessarily complex, unique (it doesn't use the common RMW code paths), and has a number of other latent bugs. To fix this, I split genCodeForShift() by leaving the non-RMW case there, and adding a genCodeForShiftRMW() function just for the RMW case. I rewrote the RMW case to use the existing emitInsRMW functions. Other related cleanups along the way: 1. I changed emitHandleMemOp to consistently set the idInsFmt field, and changed all callers to stop pre-setting or post-setting this field. This makes the API much easier to understand. I added a big header comment for the function. Now, it takes a "basic" insFmt (using ARD, AWR, or ARW forms), which might be munged to a MRD/MWR/MRW form if necessary. 2. I changed some places to always use the most derived GenTree type for all uses. For instance, if the code has "GenTreeIndir* mem = node->AsIndir()", then always use "mem" from then on, and don't use "node". I changed some functions to take more derived GenTree node types. 3. I rewrote the emitInsRMW() functions to be much simpler, and rewrote their header comments. 4. I added GenTree predicates OperIsShift(), OperIsRotate(), and OperIsShiftOrRotate(). 5. I added function genMapShiftInsToShiftByConstantIns() to encapsulate mapping from INS_shl to INS_shl_N or INS_shl_1 based on a constant. This code was in 3 different places already. 6. The change in assertionprop.cpp is simply to make JitDumps readable. In addition to fixing the bug for RyuJIT/x86, there are a small number of x64 diffs where we now generate smaller encodings for shift by 1.
2016-02-29	Add support for emitting GC-ness of the second return register for 16 byte	Lubomir Litchev	1	-40/+44
	structs. This changeset adds support for emitting the GC-ness of the second return register (RDX for System V Amd64) for multi-register return structs. It closes a hole in the GC info and resolves multiple GC stress failures. Fixes #2757.
2016-01-27	Update license headers	dotnet-bot	1	-4/+3

2015-12-11	Port of all JIT changes for .NET Framework 4.6.1 changes	Brian Sullivan	1	-2/+0
	http://blogs.msdn.com/b/dotnet/archive/2015/11/30/net-framework-4-6-1-is-now-available.aspx .NET Framework list of changes in 4.6.1 https://github.com/Microsoft/dotnet/blob/master/releases/net461/dotnet461-changes.md Additional changes including - Working ARM64 JIT compiler - Additional JIT Optimizations o Tail call recursion optimization o Array length tracking optimization o CSE for widening casts o Smaller encoding for RIP relative and absolute addresses in addressing modes o Tracked Local Variable increased to 512 o Improved handling of Intrinsics System.GetType() o Improved handling of Math intrinsics - Work for the X86 Ryu-JIT compiler [tfs-changeset: 1557101]
2015-01-30	Initial commit to populate CoreCLR repo	dotnet-bot	1	-0/+536
	[tfs-changeset: 1407945]