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path: root/src/jit/emitxarch.cpp
AgeCommit message (Expand)AuthorFilesLines
2017-05-19Merge pull request #10662 from helloguo/VectorConversionBruce Forstall1-28/+113
2017-05-15Use full move for byte registers stores in jumps. (#11570)Sergey Andreenko1-0/+6
2017-05-10add jit intrinsic support for vector conversion/narrow/widen on AMD64 and x86...helloguo1-28/+113
2017-04-22Simplify emitter's RegEncodingMike Danes1-9/+2
2017-04-07Remove RELOC_SUPPORT defineBruce Forstall1-101/+5
2017-03-13Add changes to emitMaxStackDepth and fgPtrArgCntMax to JitDump (#10130)Bruce Forstall1-0/+9
2017-03-13Build Linux altjit for x86 and amd64 (#10120)Bruce Forstall1-1/+1
2017-03-06Un-clang-format-horrible-ify emitIns_Call() and genEmitCall()Bruce Forstall1-13/+16
2017-02-23Merge pull request #9723 from fiigii/is4byteSivarv1-80/+117
2017-02-23Rewrite Is4ByteAVXInstruction() and Is4ByteSSE4Instruction()Fei Peng1-80/+117
2017-02-22Do not report FP restores in x86 epilogs.Pat Gavlin1-5/+2
2017-02-13Directly support Min/Max intrinsic for Vector<T> on SSE3_4 and above targetsFei Peng1-5/+11
2017-02-05Enable SIMD for RyuJIT/x86Bruce Forstall1-16/+4
2017-01-20[x86/Linux] Allow push/pop in funclet prolog and epilog (#9001)Jonghyun Park1-1/+6
2017-01-13Don't treat spill temps as containedCarol Eidt1-12/+11
2017-01-11Format code.Pat Gavlin1-2/+2
2017-01-11Fix #8860.Pat Gavlin1-16/+11
2016-12-01Fix recent x86 SIMD regressionsBruce Forstall1-6/+5
2016-11-30Fix x86 encoder to use 64-bit type to accumulate opcode/prefix bitsBruce Forstall1-110/+112
2016-11-29[x86/Linux] Fix extraneous parentheses (#8388)SaeHie Park1-1/+1
2016-11-29Merge pull request #8315 from mikedn/disasmPat Gavlin1-82/+41
2016-11-29Merge pull request #8291 from sivarv/sse34Sivarv1-15/+63
2016-11-29Fix various disassembly issuesMike Danes1-82/+41
2016-11-28Enable using SSE3_4 instruction set for SIMD codegen.sivarv1-15/+63
2016-11-28Factor out common stack adjustment codeBruce Forstall1-165/+69
2016-11-17Address PR feedback.Pat Gavlin1-5/+12
2016-11-16Format code.Pat Gavlin1-1/+2
2016-11-16Do not fold (ind (addr (lclVar))) in certain cases.Pat Gavlin1-1/+6
2016-10-27Initial RyuJIT x86 SIMD supportBruce Forstall1-3/+3
2016-10-21Optimize Vector<int>.Dot on AVX.sivarv1-4/+2
2016-10-17Update GC info when emitting IF_RRW_SHF.Pat Gavlin1-0/+4
2016-10-14Remove DEBUGGING_SUPPORT #ifdef (#7611)Bruce Forstall1-2/+0
2016-09-27Optimize SIMD codegen for (in)equality check against zero that produces bool ...sivarv1-1/+1
2016-09-21Reformat jit code for Windows x64Michelle McDaniel1-2/+2
2016-09-08Fix #7100Bruce Forstall1-2/+3
2016-08-26Fix DevDiv bug 255263Carol Eidt1-1/+2
2016-08-24Fix #3554. (#6880)Pat Gavlin1-1/+0
2016-08-11Reformat jit sources with clang-tidy and formatMichelle McDaniel1-4023/+3999
2016-07-29Massage code for clang-formatMichelle McDaniel1-30/+58
2016-07-26Enable multireg returns on Arm64Brian Sullivan1-3/+3
2016-07-20Support for reg optional tree temps.sivarv1-6/+37
2016-07-01Consider spilled lcl var as contained memory operands for codegen purpose.sivarv1-13/+44
2016-04-28Update RyuJIT/x86 XMM register definitions and usageBruce Forstall1-28/+39
2016-04-28Fix 3516: Change an emitter #ifdef from _TARGET_AMD64_ to !LEGACY_BACKENDBruce Forstall1-2/+3
2016-04-22Fix #3561: assert on RyuJIT x86 when generating shl by 1Bruce Forstall1-184/+214
2016-04-05Fix #1977: always create RBP chains on UnixBruce Forstall1-1/+3
2016-03-30Clarify register aliasing in the X86 encoder.Pat Gavlin1-18/+36
2016-03-25Unsuppress same-reg zero-extending mov (x64)Joseph Tremoulet1-2/+8
2016-03-14Fix some JIT disassembly issuesMike Danes1-3/+13
2016-03-07Reapply change 1578859: Add a new set of APIs for JIT configuration.Pat Gavlin1-4/+2
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