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Add cas*, ldadd*, stadd*, and swp*
Add atomic emitters
Add atomic emitter tests
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This change is the result of running clang-tidy and clang-format on jit
sources.
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This change starts the process of updating the jit code to make it ready
for being formatted by clang-format. Changes mostly include reflowing
comments that go past our column limit and moving comments around ifdefs
so clang-format does not modify the indentation. Additionally, some
header files are manually reformatted for pointer alignment and marked
as clang-format off so that we do not lose the current formatting.
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Fixes https://github.com/dotnet/coreclr/issues/3668
Currently ARM64 codegen can have reference within +/-1 MB due to encoding
restriction in `b<cond>/adr/ldr` instructions. This is normally okay
assuming each function is reasonably small, but certainly not working for large method which also
can be formed with an aggressive inlining probably like crossgen/corert scenarios.
In addition, for hot/cold code separation long address is a prerequisite
since reference can be across different regions which are arbitrary.
In fact, we need additional relocations which are not in this change yet.
In details, this supports long address for conditional jump/address loading/constant
loading operations by default while they can be shortened later by
`emitJumpDistBind()` if they can fit into the smaller encoding. Logically
those operations now can reach within +/-4GB address range.
Note I haven't extended unconditional jump in this change for simplicity
so it can reach within +/-128MB same as before.
`emitOutputLJ` is extended to finally encode these operations.
There are 3 pseudo instructions introduced. These can be expanded either
short/long form.
1. Conditional jump. See `emitIns_J()`
a. Short form(`IF_BI_0B`): `b<cond> rel_addr`
b. Long form(`IF_LARGEJMP`):
```
b<rev cond> $LABEL
b rel_addr (unconditional jump)
$LABEL:
```
2. Load label(address computation). See `emitIns_R_L()`
a. Short form(`IF_DI_1E`): `adr x, [rel_addr]`
b. Long form(`IF_LARGEADR`):
```
adrp x, [rel_page_addr]
add x, x, page_offs
```
3. Load constant (from JIT data). See `emitIns_R_C()`
a. Short form(`IF_LS_1A`): `ldr x, [rel_addr]`
b. Long form(`IF_LARGLDC`):
```
adrp x, [rel_page_addr]
ldr x, [x, page_offs]
(fmov v, x in case loading vector constant)
```
In addition, JIT data is aligned on 8 byte to be accessible from large
load. Replaced JitLargeBranches by JitLongAddress to test stress on these
operations.
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Fixes https://github.com/dotnet/coreclr/issues/4350
Fixes https://github.com/dotnet/coreclr/issues/4615
This is a bit large change across VM/Zap/JIT to properly support crossgen
scenario.
1. Fix incorrect `ldr` encoding with size.
2. Enforce JIT data following JIT code per method by allocating them together.
This guarantees correct PC-relative encoding for such constant data access
without fix-up.
3. For the general fix-up data acceess, use `adrp/add` instruction pairs with fix-ups.
Two more relocations types are implemented in all sides.
4. Interface dispatch stub is now implemented which is needed for
interface call for crossgen.
I've verified hello world runs with mscorlib.ni.dll.
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This fixes https://github.com/dotnet/coreclr/issues/3738.
The fix I made in
https://github.com/dotnet/coreclr/commit/4dfd323dab88b902fc9479efa60cb5d6b7659e94
used 3rd/4th operand to keep GC info, which actually conflicts with
address field which is unioned with these operands.
So, I go back to the original fix that I proposed below:
Indirect call (```br``` or ```blr```) target is encoded with a register
which the first operand internally represents.
Unfortunately, call sites use the first two operands to hold GC callee-save registers.
So, this GC register information was overridden by the call target operand
in the indirect(virtual) call sites.
The fix is to split branch instruction categories for these two instructions
while keeping ```ret``` same as before. They internally use the third
operand to encode the target since the first two are used for GC info.
The reason I didn't change ```ret``` is because the return instruction
is created as a small instruction (not using operand 3 and more).
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[tfs-changeset: 1407945]
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