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path: root/src/jit/codegenlinear.cpp
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2018-12-14Merge pull request #21535 from CarolEidt/Fix21500Carol Eidt1-7/+22
2018-12-13Update var life for multireg localCarol Eidt1-8/+23
2018-12-10Eliminate GenTreeRegVar and GT_REG_VAR and RegVar (#18317)Julius R Friedman1-12/+0
2018-11-05Fix SP check for x64/x86, remove for arm32/arm64Bruce Forstall1-4/+16
2018-09-06Merge pull request #19296 from mikedn/cast-cgCarol Eidt1-1/+119
2018-09-06Clean CodeGen::genEmitCall (#19804)Sergey Andreenko1-4/+2
2018-09-06Make cast classification arch independentMike Danes1-0/+118
2018-09-06Refactor genIntToIntCast on ARMMike Danes1-1/+1
2018-08-28Handle multiReg COPYCarol Eidt1-0/+54
2018-08-27Deal with compilation warnings in JIT in cross-bitness scenario (#19590)Egor Chesakov1-5/+5
2018-08-22define FMT_BB as "BB%02u" and use it uniformly in the codebaseBrian Sullivan1-2/+2
2018-06-30Move temp info from Compiler to RegSetMike Danes1-5/+5
2018-06-29Corrected a few typos in the documentation and comments (#18706)Phil Garcia1-3/+3
2018-06-15Use correct field offset in genPutArgStkFieldList (#18483)Carol Eidt1-4/+5
2018-06-14[Windows|Arm64|Vararg] Add FEATURE_ARG_SPLIT (#18346)Jarret Shook1-5/+9
2018-06-12Unify struct arg handling (#18358)Carol Eidt1-0/+39
2018-06-02JIT: Eliminate RegTracker (#18179) (#18230)Andrew Au1-1/+5
2018-05-22Remove JIT LEGACY_BACKEND code (#18064)Bruce Forstall1-34/+2
2018-04-13Insert int3 after non-returning calls at the end of basic blocks. (#17535)Eugene Rozenfeld1-0/+16
2018-03-27[ARM64] Fix UnspillReg instruction generationDebayan Ghosh1-4/+9
2018-02-03Updating the HWIntrinsic codegen to support marking LoadVector128 and LoadAli...Tanner Gooding1-0/+4
2018-01-31Delete GenTreePtr. (#16027)Sergey Andreenko1-5/+5
2017-11-10[Arm64] Do not change vector load register sizeSteve MacLean1-1/+1
2017-11-06Merge pull request #14024 from mikedn/long-cast-commCarol Eidt1-0/+6
2017-10-11Cleanup of Lowering & LsraInfoCarol Eidt1-9/+4
2017-09-28ignore GT_ARGPLACE before gtUseNum check. (#14233)Sergey Andreenko1-1/+2
2017-09-16Move genLongToIntCast call to codegenlinearMike Danes1-0/+6
2017-09-12Merge pull request #13715 from CarolEidt/LsraInfoInLsraCarol Eidt1-1/+1
2017-09-06Jit doesn't reload shift index if it was spilled to rcx. (#13757)Sergey Andreenko1-0/+1
2017-08-30Do TreeNodeInfoInit in buildIntervalsCarol Eidt1-1/+1
2017-08-10Merge pull request #13306 from hseok-oh/ryujit/fix_13156Carol Eidt1-1/+1
2017-08-11Fix genSpillVarHyeongseok Oh1-1/+1
2017-08-10[RyuJIT/armel] Introduce GetRegCount() for MultiRegOpHanjoung Lee1-2/+2
2017-08-07[RyuJIT/armel] Each reg gets own SpillFlag for MultiRegOpHanjoung Lee1-0/+42
2017-07-11Delete bitset iterators defines (#12642)Sergey Andreenko1-2/+4
2017-06-28[RyuJIT/ARM32] Enable passing large split struct argument (#12050)Hyeongseok Oh1-0/+72
2017-06-08Merge pull request #11901 from CarolEidt/RegValCarol Eidt1-11/+0
2017-06-07Run the LIR checker before codegen.Pat Gavlin1-0/+2
2017-06-07Make containedness explicitCarol Eidt1-11/+0
2017-05-26Fix BitSetUint64, clean and improve the surrounding code. (#11721)Sergey Andreenko1-3/+3
2017-05-22Refactor genCodeForTreeNode for xarch to match arm32/arm64Bruce Forstall1-0/+35
2017-05-19Improve BitVecOps<>::Iter::NextElem (#11696)Bruce Forstall1-2/+2
2017-05-19Remove `GTF_REVERSE_OPS` from LIR. (#10698)Pat Gavlin1-59/+11
2017-05-09Fix issue #11446. (#11455)Pat Gavlin1-1/+1
2017-04-27Do not report out-of-order consuming if node wasn't consumed at allMikhail Skvortcov1-1/+5
2017-03-12Move adjustments to genStackLevel into functionsBruce Forstall1-2/+2
2017-03-06Un-clang-format-horrible-ify emitIns_Call() and genEmitCall()Bruce Forstall1-17/+47
2017-02-09Address the feedback.Mikhail Skvortcov1-0/+4
2017-02-06Remove unnecessary parameter to genCallFinally()Bruce Forstall1-4/+3
2017-01-17Remove unused codeMike Danes1-6/+0
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