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path: root/src/jit/codegenarmarch.cpp
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2019-03-20Adding a flag to able/disable scope info (#23298)Brian Bohe1-1/+2
* Flag USING_SCOPE_INGO definition * Enclosing siScope's related functions uses with USING_SCOPE_INFO flag definition check * Encapsulating genSetScopeInfo when using siVarScope * Moving comment inside flag defined block * Include siScope/psiScope functions only when flag USING_SCOPE_INFO is defined * Disable scope info * Typo * Adding comment flag name on #endif * Remove redundant access levels/flags * Repeating last accessibility level in case flag is disabled * Setting use of siScope and psiScope as default way of reporting variable homes
2019-03-12Arm64: Implement JMP call for HFA register argumentsBruce Forstall1-31/+53
Add the code to load up HFA register arguments into their correct registers before a JMP call. Removes remaining NYI. Fixes #23147 Add a test case with several variants of HFA and JMP call.
2019-03-08JIT: rework codegen for Arm64 SIMD Extract/Insert intrinsics (#23114)Andy Ayers1-6/+4
Add an up-front bounds check during importation instead of waiting until codegen. Mirrors what we do for similar cases on xarch. Closes #20260.
2019-02-19Fix formattingBrian Sullivan1-1/+1
2019-02-19Correct the assert to add R8 as a potential valid registerBrian Sullivan1-6/+8
Also fix the calls to RemoveElemD to use lvVarIndex Re-enable the interop tests that were failing on ARM64
2019-02-12JIT: change how we block gc refs from callee saves for inline pinvokes (#22477)Andy Ayers1-0/+7
Add a new marker instruction that we emit once we've enabled preepmtive gc in the inline pinvoke method prolog. Use that to kill off callee saves registers with GC references, instead of waiting until the call. This closes a window of vulnerability we see in GC stress where if a stress interrupt happens between the point at which we enable preeemptive GC and the point at which we make the call, we may report callee saves as GC live when they're actually dead. Closes #19211.
2019-01-30Remove GTF_ADDR_ONSTACK and IsVarAddr.Eugene Rozenfeld1-2/+4
IsVarAddr was checking GTF_ADDR_ONSTACK to determine if the GT_ADDR node is an address of a local. This change removes both GTF_ADDR_ONSTACK and IsVarAddr and uses IsLocalAdrExpr instead. IsLocalAddrExpr uses opcodes to determine if GT_ADDR node is a local address. GTF_ADDR_ONSTACK flag is ancient, added before 2002 so I couldn't find the checkin that introduced it. I changed the assert to a check and an assignment since simplifications inside fgMorphArgs between https://github.com/dotnet/coreclr/blob/1a1e4c4d5a8030cb8d82a2e5b06c2ab357b92534/src/jit/morph.cpp#L3709 (which causes https://github.com/dotnet/coreclr/blob/1a1e4c4d5a8030cb8d82a2e5b06c2ab357b92534/src/jit/morph.cpp#L3057) and https://github.com/dotnet/coreclr/blob/1a1e4c4d5a8030cb8d82a2e5b06c2ab357b92534/src/jit/morph.cpp#L3790 may result in more GT_ADDR nodes recognized by IsLocalAdrExpr. x86 and x64 pmi frameworks had no code diffs and some gcinfo reductions (15 methods with gcinfo diffs in x86). Fixes #22190.
2019-01-10Merge pull request #17733 from mikedn/cc-cond2Brian Sullivan1-197/+62
Expand GT_JCC/SETCC condition support
2019-01-09Merge pull request #20772 from mikedn/ir-cleanupBruce Forstall1-2/+1
Some IR cleanup
2018-12-13Update var life for multireg localCarol Eidt1-0/+1
When a multi-reg var is defined by a call, but doesn't currently reside in a register, we must still update liveness. Fix #21500
2018-12-05Refactor genAllocLclFrame into two architecture-specific functions (#21074)Egor Chesakov1-0/+134
2018-11-10Remove genJumpKindForOperMike Danes1-5/+4
2018-11-10Delete dead codeMike Danes1-123/+0
2018-11-10Move genCodeForSetcc to codegenlinear.cppMike Danes1-12/+10
2018-11-10Reimplement genCodeForJumpTrue using GenConditionMike Danes1-35/+1
2018-11-10Add support for floating point conditionsMike Danes1-40/+28
2018-11-10Introduce GenConditionMike Danes1-11/+48
2018-11-03Delete GenTreeLabelMike Danes1-2/+1
This is only used to hold a pointer to a BasicBlock for GenTreeBoundsChk and GenTreeIndexAddr. This doesn't serve any purpose and it does not behave like a real operand (e.g. it's not included in the linear order).
2018-10-11Fix for CoreRT issue Assertion slot != NO_REVERSE_PINVOKE_FRAME' failed #6253Sergey Ignatov1-0/+8
2018-09-17Merge pull request #15657 from mikedn/fp-divmul-binaryCarol Eidt1-1/+1
Move FP DIV/MUL handling to genCodeForBinary
2018-09-12Arm: Correctly handle multi-reg COPYCarol Eidt1-44/+63
Fix #19448
2018-09-08Move FP DIV/MUL handling to genCodeForBinaryMike Danes1-1/+1
Floating point (SSE) MUL/DIV instructions have the same formats as ADD/SUB but they're handled by genCodeForMul and genCodeForDivMod. At least in the case of division this results in duplicated logic being required in genCodeForDivMod.
2018-09-06Make cast classification arch independentMike Danes1-135/+75
2018-09-06Get rid of Lowering::getCastDescriptionMike Danes1-3/+3
2018-09-06Improve ARM genIntCastOverflowCheckMike Danes1-73/+66
2018-09-06Refactor genIntToIntCast on ARMMike Danes1-79/+66
2018-09-06Extract cast overflow check ARM codegen to genIntCastOverflowCheckMike Danes1-78/+106
2018-08-27Deal with compilation warnings in JIT in cross-bitness scenario (#19590)Egor Chesakov1-1/+1
* Fix warnings due to "strlen return type is size_t" in src/jit/emitarm.cpp src/jit/unwindarm.cpp * Use ptrdiff_t disp in emitter::emitOutputInstr in src/jit/emitarm.cpp * Compiler::gtHashValue should depend on host-bitness in src/jit/gentree.cpp * Simplify checking using ImmedValNeedsReloc() in src/jit/lowerarmarch.cpp * Use target_ssize_t immVal in Lowering::IsContainableImmed in src/jit/lowerarmarch.cpp * Remove int offs and use BYTE* addr and %p specifier in emitter::emitDispInsHelp in IF_T2_J3 case in src/jit/emitarm.cpp * Cast gtIconVal to target_size_t in CodeGen::genLclHeap in src/jit/codegenarm.cpp * Use int argSize in CodeGen::genEmitCall in src/jit/codegen.h src/jit/codegenlinear.cpp * Use ssize_t disp in emitter::emitIns_Call in src/jit/emitarm.cpp src/jit/emitarm.h * Use int argSize in emitter::emitIns_Call in src/jit/emitarm.cpp src/jit/emitarm.h * Use target_size_t return type in Compiler::eeGetPageSize Compiler::getVeryLargeFrameSize in src/jit/codegencommon.cpp src/jit/compiler.h * Cast gtIconVal to unsigned in CodeGen::genCodeForShift CodeGen::genCodeForShiftLong in src/jit/codegenarm.cpp src/jit/codegenarmarch.cpp * Cast gtIconVal to unsigned in DecomposeLongs::DecomposeRotate in src/jit/decomposelongs.cpp * Use unsigned size in CodeGen::genConsumePutStructArgStk in src/jit/codegenlinear.cpp * Use target_ssize_t stmImm in cast in CodeGen::genZeroInitFrame in src/jit/codegencommon.cpp * Cast to target_ssize_t in Compiler::gtSetEvalOrder in src/jit/gentree.cpp * Address PR feedbask - use dspPtr(addr) in src/jit/emitarm.cpp
2018-08-22Handle multireg copies correctly (#19588)Carol Eidt1-3/+16
* Handle multireg copies correctly Fix #19029
2018-07-18Arm64: Fix handling of IP0 & IP1Carol Eidt1-0/+1
These are sometimes mandated to be allocated to certain nodes, but they were not in the list of allocatable registers (REG_VAR_ORDER). This led to special handling in LSRA, which, it turns out, was incomplete. This resulted in failures for JitStressRegs=0x200. Based on the discussion in #14607, this adds IP0 to RBM_CALLEE_TRASH_NOGC, and fixes the REG_VAR_ORDER. Fix #14607, Fix #16359, Fix #17861
2018-06-14[Windows|Arm64|Vararg] Add FEATURE_ARG_SPLIT (#18346)Jarret Shook1-6/+8
* [ARM64|Windows|Vararg] Add FEATURE_ARG_SPLIT Enable splitting >8 byte <= 16 byte structs for arm64 varargs between x7 and virtual stack slot 0. * Force notHfa for vararg methods * Correctly pass isVararg * Correct var name
2018-06-13[Windows|Arm64|VarArgs] Correctly pass HFA arguments (#18364)Jarret Shook1-2/+2
* Fix passing HFA of two floats to vararg methods Previously, the type would be reported as HFA and enregistered; however, this is not correct, as arm64 varargs abi requires passing using int registers. * Address linux build issue * Apply final format patch * Add _TARGET_WINDOWS_
2018-06-12Unify struct arg handling (#18358)Carol Eidt1-36/+1
* Unify struct arg handling Eliminate unnecessary struct copies, especially on Linux, and reduce code duplication. Across all targets, use GT_FIELD_LIST to pass promoted structs on stack, and avoid requiring a copy and/or marking `lvDoNotEnregister` for those cases. Unify the specification of multi-reg args: - numRegs now indicates the actual number of reg args (not the size in pointer-size units) - regNums contains all the arg register numbers
2018-06-06Fix ARM cast codegen (#18063)mikedn1-63/+52
* Fix ARM cast codegen ARM cast codegen is rather convoluted and sometimes does the wrong thing by applying GTF_UNSIGNED to the destination type even though this flag is only about the source type. * Add more conversion tests These tests are intended to support casts with contained operands. They're also useful to catch issues caused by load nodes having small types and generally improve test coverage for casts.
2018-06-04Cleanup LOCKADD handlingMike Danes1-1/+0
LOCKADD nodes are generated rather early and there's no reason for that: * The CORINFO_INTRINSIC_InterlockedAdd32/64 intrinsics are not actually used. Even if they would be used we can still import them as XADD nodes and rely on lowering to generate LOCKADD when needed. * gtExtractSideEffList transforms XADD into LOCKADD but this can be done in lowering. LOCKADD is an XARCH specific optimization after all. Additionally: * Avoid the need for special handling in LSRA by making GT_LOCKADD a "no value" oper. * Split LOCKADD codegen from XADD/XCHG codegen, attempting to use the same code for all 3 just makes things more complex. * The address is always in a register so there's no real need to create an indir node on the fly, the relevant emitter functions can be called directly. The last point above is actually a CQ issue - we always generate `add [reg], imm`, more complex address modes are not used. Unfortunately this problem starts early, when the importer spills the address to a local variable. If that ever gets fixed then we'll could probably generate a contained LEA in lowering.
2018-05-22Remove JIT LEGACY_BACKEND code (#18064)Bruce Forstall1-4/+0
Remove JIT LEGACY_BACKEND code All code related to the LEGACY_BACKEND JIT is removed. This includes all code related to x87 floating-point code generation. Almost 50,000 lines of code have been removed. Remove legacyjit/legacynonjit directories Remove reg pairs Remove tiny instruction descriptors Remove compCanUseSSE2 (it's always true) Remove unused FEATURE_FP_REGALLOC
2018-05-15[Arm64] Fix stack struct arg packingSteve MacLean1-0/+16
2018-05-08Handle SIMD field of GT_FIELD_LIST in codegen.Carol Eidt1-12/+12
Add header to test case.
2018-05-02Fix for Issue 17823Brian Sullivan1-63/+51
Ensure that any byrefs created in genCodeForIndexAddr cannot point outside of the array Used the scaled add instructions for more powers of two Only use the safe byref sequence when generating fully interruptible code.
2018-04-19Account for copied bytes in struct copy loop when generating GT_PUTARG_STK code.Aditya Mandaleeka1-1/+1
2018-04-03Remove most ARM NYI (#17365)Bruce Forstall1-13/+17
* Remove most ARM NYI Convert most existing ARM NYI either to asserts or remove the code entirely. A few NYI are left, including: 1. GT_BITCAST from 'int' to 'float' 2. initblk unrolling is unimplemented: https://github.com/dotnet/coreclr/issues/16349 3. SIMD-related NYI (SIMD is currently unimplemented)
2018-03-05[ARM32] RyuJIT support for profiler ELT callbacks (#16728)Sergey Andreenko1-3/+0
* add assert that argReg was PreSpilled * genProfilingEnterCallback for RyuJit arm * fix genProfilingLeaveCallback for RyuJit arm * call genProfilingLeaveCallback for arm from genJmpMethod
2018-01-31Delete GenTreePtr. (#16027)Sergey Andreenko1-57/+57
* jit sources: Each local pointer variable must be declared on its own line. Implement https://github.com/dotnet/coreclr/blob/master/Documentation/coding-guidelines/clr-jit-coding-conventions.md#101-pointer-declarations Each local pointer variable must be declared on its own line. * add constGenTreePtr * delete GenTreePtr * delete constGenTreePtr * fix arm
2018-01-26[Arm64] Initial HWIntrinsic implementationSteve MacLean1-0/+6
2018-01-24Delete Ptr typedefs from jit src. (#15983)Sergey Andreenko1-2/+2
* delete fgArgInfoPtr * delete treeLstPtr * delete treeStmtLstPtr * delete fgArgTabEntryPtr * delete BasicBlockPtr
2017-12-20Remove unused TYP_ARRAY/PTR/FUNC (#15529)mikedn1-1/+1
2017-12-06Fix GT_FIELD_LIST double passed as intCarol Eidt1-6/+24
Correctly handle a double field passed in int regs under a `GT_FIELD_LIST`, especially in the case of a `PutArgSplit`. Also, reduce the spew of dump info when `COMPlus_JitStressModeNames` or `COMPlus_JitStressModeNamesNot` are set. Enhance the dumping of `fgArgInfo`. Fix #15325
2017-12-01Merge pull request #15281 from sdmaclea/PR-ARM64-Fix-UNROLL_LIMITBruce Forstall1-1/+1
[Arm64] Fix UNROLL_LIMIT logic
2017-12-01Merge pull request #15275 from ↵Bruce Forstall1-0/+2
sdmaclea/PR-ARM64-SIMD-genMultiRegCallStoreToLocal-produceReg [Arm64] SIMD genMultiRegCallStoreToLocal add missing produceReg
2017-11-29[RyuJit] Delete contained workaround. (#15257)Sergey Andreenko1-30/+0
* Move CodeGen::indirForm and IntForm to common. * GenTreeFieldList: SetContained only for the head. * delete the workaround. * move check from isContained to CheckLIR `isContained` can't determinate does node has user or not. Move this check to the appropriate place. * check that SetContained and IsContained are consistent.
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