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path: root/src/jit/codegenarm64.cpp
AgeCommit message (Expand)AuthorFilesLines
2018-04-15[Arm64] Add full barrier after locking operations (#17567)Steve MacLean1-8/+7
2018-03-30Tighten arm32/arm64 write barrier kill reg setsBruce Forstall1-30/+7
2018-03-07[RyuJIt] Clean and fix gen return (#16725)Sergey Andreenko1-61/+26
2018-02-28Refactor the signature of genGetSimdInsOpt to use emitAttrBrian Sullivan1-77/+47
2018-02-28ARM64 SHA1 Crypto intrinsics implementationDebayan Ghosh1-0/+170
2018-02-28ARM64 Aes Crypto intrinsics implementationDebayan Ghosh1-0/+51
2018-02-14[Arm64] Additional Insert commentsSteve MacLean1-1/+9
2018-02-12Insert contain extractSteve MacLean1-1/+4
2018-02-09[Arm64] Implement Simd.InsertSteve MacLean1-1/+99
2018-02-01[Arm64] Add Lower Compare Zero commentsSteve MacLean1-1/+1
2018-02-01[Arm64] HWIntrinsic codegen function headersSteve MacLean1-0/+65
2018-02-01[Arm64] Implement Simd.SetAllVector*Steve MacLean1-0/+53
2018-02-01[Arm64] Implement Simd.BitwiseSelectSteve MacLean1-1/+69
2018-02-01[Arm64] Implement Simd.ExtractSteve MacLean1-1/+183
2018-01-31Delete GenTreePtr. (#16027)Sergey Andreenko1-40/+40
2018-01-26[Arm64] Initial HWIntrinsic implementationSteve MacLean1-0/+146
2018-01-24Disable the ConvertToUInt intrinsics by removing them from simdintrinsiclist.hCarol Eidt1-9/+1
2018-01-15[Arm64] Use is16ByteSteve MacLean1-23/+23
2017-12-13get rid of TYP_CHARFei Peng1-3/+3
2017-12-11Merge pull request #15478 from BruceForstall/FixArmLocallocBruce Forstall1-6/+6
2017-12-11Fix arm/arm64 locallocBruce Forstall1-6/+6
2017-12-08[Arm64] SIMDIntrinsicGetItem contain mem op1Steve MacLean1-21/+85
2017-11-28[Arm64] Use REG_IP1 for genEpilogRestoreReg*Steve MacLean1-4/+4
2017-11-20Merge pull request #15120 from sdmaclea/PR-ARM64-SIMD-SIMD12-genCodeForStoreLclCarol Eidt1-0/+59
2017-11-20[Arm64] SIMD12 genCodeForStoreLcl*Steve MacLean1-0/+59
2017-11-20[Arm64] SIMD fix SIMDIntrinsicSet* op2 lifeSteve MacLean1-0/+1
2017-11-14Merge pull request #14975 from sdmaclea/PR-SIMD-genSIMDIntrinsicInit-0Carol Eidt1-3/+2
2017-11-14Merge pull request #14976 from sdmaclea/PR-SIMD-genCodeForStoreLclVar-0Carol Eidt1-0/+10
2017-11-13Merge pull request #14944 from sdmaclea/PR-ARM64-SIMD-Partial-Callee-Save-SIMD12Carol Eidt1-2/+4
2017-11-10[Arm64] Do not change vector load register sizeSteve MacLean1-3/+3
2017-11-10[ARM64] SIMD genCodeForStoreLclVar zero initSteve MacLean1-0/+10
2017-11-10[ARM64] genSIMDIntrinsicInit contain 0Steve MacLean1-3/+2
2017-11-10[ARM64] SIMD Partial Callee Save SIMD12Steve MacLean1-2/+4
2017-11-07Merge pull request #14887 from sdmaclea/PR-ARM64-genSIMDIntrinsicNarrow-WidenCarol Eidt1-12/+47
2017-11-06Merge pull request #14735 from mikedn/emit-const-cleanupCarol Eidt1-5/+4
2017-11-06[Arm64] genSIMDIntrinsicNarrow/WidenSteve MacLean1-12/+47
2017-11-03[Arm64] SIMD12 Indirect Load/StoreSteve MacLean1-0/+92
2017-11-02Merge pull request #14809 from sdmaclea/PR-ARM64-genSIMDIntrinsicGetItemBruce Forstall1-5/+29
2017-11-02[Arm64] genSIMDIntrinsicRelOpSteve MacLean1-0/+8
2017-11-02[Arm64] SIMDIntrinsicGetItemSteve MacLean1-5/+29
2017-11-01[Arm64] Fix genSIMDIntrinsicDotProductSteve MacLean1-2/+9
2017-10-31[Arm64] Add SIMD codegenSteve MacLean1-0/+975
2017-10-28Change emitFltOrDblConst parametersMike Danes1-5/+4
2017-10-24Merge pull request #14658 from mikedn/legacy-reg-trackBruce Forstall1-1/+0
2017-10-24Ifdef out legacy RegTracker codeMike Danes1-1/+0
2017-10-20[Arm64] Add SIMD emittersSteve MacLean1-0/+184
2017-10-17Arm64: Use op2 type for LOCKADDCarol Eidt1-5/+6
2017-10-11Refactor code for constant handles that reference opts.compReloc to use Immed...Brian Sullivan1-2/+1
2017-10-06Fix comments per reviewSteve MacLean1-2/+7
2017-10-05[Arm64] Respond to feedbackSteve MacLean1-19/+31
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