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path: root/src/jit/hwintrinsiccodegenxarch.cpp
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Diffstat (limited to 'src/jit/hwintrinsiccodegenxarch.cpp')
-rw-r--r--src/jit/hwintrinsiccodegenxarch.cpp21
1 files changed, 11 insertions, 10 deletions
diff --git a/src/jit/hwintrinsiccodegenxarch.cpp b/src/jit/hwintrinsiccodegenxarch.cpp
index d21d2946c9..4d63bef6ef 100644
--- a/src/jit/hwintrinsiccodegenxarch.cpp
+++ b/src/jit/hwintrinsiccodegenxarch.cpp
@@ -323,7 +323,8 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
switch (isa)
{
- case InstructionSet_Base:
+ case InstructionSet_Vector128:
+ case InstructionSet_Vector256:
genBaseIntrinsic(node);
break;
case InstructionSet_SSE:
@@ -1226,8 +1227,8 @@ void CodeGen::genBaseIntrinsic(GenTreeHWIntrinsic* node)
switch (intrinsicId)
{
- case NI_Base_Vector128_CreateScalarUnsafe:
- case NI_Base_Vector256_CreateScalarUnsafe:
+ case NI_Vector128_CreateScalarUnsafe:
+ case NI_Vector256_CreateScalarUnsafe:
{
if (varTypeIsIntegral(baseType))
{
@@ -1252,8 +1253,8 @@ void CodeGen::genBaseIntrinsic(GenTreeHWIntrinsic* node)
break;
}
- case NI_Base_Vector128_ToScalar:
- case NI_Base_Vector256_ToScalar:
+ case NI_Vector128_ToScalar:
+ case NI_Vector256_ToScalar:
{
assert(varTypeIsFloating(baseType));
@@ -1271,7 +1272,7 @@ void CodeGen::genBaseIntrinsic(GenTreeHWIntrinsic* node)
break;
}
- case NI_Base_Vector128_ToVector256:
+ case NI_Vector128_ToVector256:
{
// ToVector256 has zero-extend semantics in order to ensure it is deterministic
// We always emit a move to the target register, even when op1Reg == targetReg,
@@ -1291,8 +1292,8 @@ void CodeGen::genBaseIntrinsic(GenTreeHWIntrinsic* node)
break;
}
- case NI_Base_Vector128_ToVector256Unsafe:
- case NI_Base_Vector256_GetLower:
+ case NI_Vector128_ToVector256Unsafe:
+ case NI_Vector256_GetLower:
{
if (op1->isContained() || op1->isUsedFromSpillTemp())
{
@@ -1306,8 +1307,8 @@ void CodeGen::genBaseIntrinsic(GenTreeHWIntrinsic* node)
break;
}
- case NI_Base_Vector128_Zero:
- case NI_Base_Vector256_Zero:
+ case NI_Vector128_Zero:
+ case NI_Vector256_Zero:
{
assert(op1 == nullptr);
emit->emitIns_SIMD_R_R_R(ins, attr, targetReg, targetReg, targetReg);