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Diffstat (limited to 'src/jit/emitxarch.cpp')
-rw-r--r--src/jit/emitxarch.cpp354
1 files changed, 155 insertions, 199 deletions
diff --git a/src/jit/emitxarch.cpp b/src/jit/emitxarch.cpp
index be5cefbfea..b495d015d6 100644
--- a/src/jit/emitxarch.cpp
+++ b/src/jit/emitxarch.cpp
@@ -48,6 +48,15 @@ bool IsSSEOrAVXInstruction(instruction ins)
#endif // !FEATURE_AVX_SUPPORT
}
+bool IsAVXOnlyInstruction(instruction ins)
+{
+#ifdef FEATURE_AVX_SUPPORT
+ return (ins >= INS_FIRST_AVX_INSTRUCTION && ins <= INS_LAST_AVX_INSTRUCTION);
+#else
+ return false;
+#endif
+}
+
bool emitter::IsAVXInstruction(instruction ins)
{
#ifdef FEATURE_AVX_SUPPORT
@@ -81,9 +90,11 @@ bool emitter::IsThreeOperandBinaryAVXInstruction(instruction ins)
ins == INS_minsd || ins == INS_divps || ins == INS_divpd || ins == INS_maxps || ins == INS_maxpd ||
ins == INS_maxss || ins == INS_maxsd || ins == INS_andnps || ins == INS_andnpd || ins == INS_paddb ||
ins == INS_paddw || ins == INS_paddd || ins == INS_paddq || ins == INS_psubb || ins == INS_psubw ||
- ins == INS_psubd || ins == INS_psubq || ins == INS_pmuludq || ins == INS_pxor || ins == INS_pmaxub ||
- ins == INS_pminub || ins == INS_pmaxsw || ins == INS_pminsw || ins == INS_insertps ||
- ins == INS_vinsertf128 || ins == INS_punpckldq || ins == INS_phaddd);
+ ins == INS_psubd || ins == INS_psubq || ins == INS_pmuludq || ins == INS_pxor || ins == INS_insertps ||
+ ins == INS_vinsertf128 || ins == INS_punpckldq || ins == INS_phaddd || ins == INS_pminub ||
+ ins == INS_pminsw || ins == INS_pminsb || ins == INS_pminsd || ins == INS_pminuw || ins == INS_pminud ||
+ ins == INS_pmaxub || ins == INS_pmaxsw || ins == INS_pmaxsb || ins == INS_pmaxsd || ins == INS_pmaxuw ||
+ ins == INS_pmaxud);
}
// Returns true if the AVX instruction is a move operator that requires 3 operands.
@@ -106,16 +117,9 @@ bool emitter::IsThreeOperandMoveAVXInstruction(instruction ins)
//
// Note that this should be true for any of the instructions in instrsXArch.h
// that use the SSE38 or SSE3A macro.
-//
-// TODO-XArch-Cleanup: This is a temporary solution for now. Eventually this
-// needs to be addressed by expanding instruction encodings.
bool emitter::Is4ByteAVXInstruction(instruction ins)
{
- return UseAVX() &&
- (ins == INS_dpps || ins == INS_dppd || ins == INS_insertps || ins == INS_pcmpeqq || ins == INS_pcmpgtq ||
- ins == INS_vbroadcastss || ins == INS_vbroadcastsd || ins == INS_vpbroadcastb || ins == INS_vpbroadcastw ||
- ins == INS_vpbroadcastd || ins == INS_vpbroadcastq || ins == INS_vextractf128 || ins == INS_vinsertf128 ||
- ins == INS_pmulld || ins == INS_ptest || ins == INS_phaddd);
+ return UseAVX() && (IsSSE4Instruction(ins) || IsAVXOnlyInstruction(ins)) && EncodedBySSE38orSSE3A(ins);
}
#endif // FEATURE_AVX_SUPPORT
@@ -134,8 +138,7 @@ bool emitter::Is4ByteSSE4Instruction(instruction ins)
// On legacy backend SSE3_4 is not enabled.
return false;
#else
- return UseSSE3_4() && (ins == INS_dpps || ins == INS_dppd || ins == INS_insertps || ins == INS_pcmpeqq ||
- ins == INS_pcmpgtq || ins == INS_pmulld || ins == INS_ptest || ins == INS_phaddd);
+ return UseSSE3_4() && IsSSE4Instruction(ins) && EncodedBySSE38orSSE3A(ins);
#endif
}
@@ -739,7 +742,10 @@ void emitter::emitMarkStackLvl(unsigned stackLevel)
emitCurStackLvl = emitCurIG->igStkLvl = stackLevel;
if (emitMaxStackDepth < emitCurStackLvl)
+ {
+ JITDUMP("Upping emitMaxStackDepth from %d to %d\n", emitMaxStackDepth, emitCurStackLvl);
emitMaxStackDepth = emitCurStackLvl;
+ }
}
#endif
@@ -938,72 +944,6 @@ inline size_t insCode(instruction ins)
/*****************************************************************************
*
- * Returns the "[r/m], 32-bit icon" encoding of the given CPU instruction.
- */
-
-inline size_t insCodeMI(instruction ins)
-{
- // clang-format off
- const static
- size_t insCodesMI[] =
- {
- #define INST0(id, nm, fp, um, rf, wf, mr )
- #define INST1(id, nm, fp, um, rf, wf, mr )
- #define INST2(id, nm, fp, um, rf, wf, mr, mi ) mi,
- #define INST3(id, nm, fp, um, rf, wf, mr, mi, rm ) mi,
- #define INST4(id, nm, fp, um, rf, wf, mr, mi, rm, a4 ) mi,
- #define INST5(id, nm, fp, um, rf, wf, mr, mi, rm, a4, rr) mi,
- #include "instrs.h"
- #undef INST0
- #undef INST1
- #undef INST2
- #undef INST3
- #undef INST4
- #undef INST5
- };
- // clang-format on
-
- assert((unsigned)ins < sizeof(insCodesMI) / sizeof(insCodesMI[0]));
- assert((insCodesMI[ins] != BAD_CODE));
-
- return insCodesMI[ins];
-}
-
-/*****************************************************************************
- *
- * Returns the "reg, [r/m]" encoding of the given CPU instruction.
- */
-
-inline size_t insCodeRM(instruction ins)
-{
- // clang-format off
- const static
- size_t insCodesRM[] =
- {
- #define INST0(id, nm, fp, um, rf, wf, mr )
- #define INST1(id, nm, fp, um, rf, wf, mr )
- #define INST2(id, nm, fp, um, rf, wf, mr, mi )
- #define INST3(id, nm, fp, um, rf, wf, mr, mi, rm ) rm,
- #define INST4(id, nm, fp, um, rf, wf, mr, mi, rm, a4 ) rm,
- #define INST5(id, nm, fp, um, rf, wf, mr, mi, rm, a4, rr) rm,
- #include "instrs.h"
- #undef INST0
- #undef INST1
- #undef INST2
- #undef INST3
- #undef INST4
- #undef INST5
- };
- // clang-format on
-
- assert((unsigned)ins < sizeof(insCodesRM) / sizeof(insCodesRM[0]));
- assert((insCodesRM[ins] != BAD_CODE));
-
- return insCodesRM[ins];
-}
-
-/*****************************************************************************
- *
* Returns the "AL/AX/EAX, imm" accumulator encoding of the given instruction.
*/
@@ -1070,6 +1010,86 @@ inline size_t insCodeRR(instruction ins)
// clang-format off
const static
+size_t insCodesRM[] =
+{
+ #define INST0(id, nm, fp, um, rf, wf, mr )
+ #define INST1(id, nm, fp, um, rf, wf, mr )
+ #define INST2(id, nm, fp, um, rf, wf, mr, mi )
+ #define INST3(id, nm, fp, um, rf, wf, mr, mi, rm ) rm,
+ #define INST4(id, nm, fp, um, rf, wf, mr, mi, rm, a4 ) rm,
+ #define INST5(id, nm, fp, um, rf, wf, mr, mi, rm, a4, rr) rm,
+ #include "instrs.h"
+ #undef INST0
+ #undef INST1
+ #undef INST2
+ #undef INST3
+ #undef INST4
+ #undef INST5
+};
+// clang-format on
+
+// Returns true iff the give CPU instruction has an RM encoding.
+inline bool hasCodeRM(instruction ins)
+{
+ assert((unsigned)ins < sizeof(insCodesRM) / sizeof(insCodesRM[0]));
+ return ((insCodesRM[ins] != BAD_CODE));
+}
+
+/*****************************************************************************
+ *
+ * Returns the "reg, [r/m]" encoding of the given CPU instruction.
+ */
+
+inline size_t insCodeRM(instruction ins)
+{
+ assert((unsigned)ins < sizeof(insCodesRM) / sizeof(insCodesRM[0]));
+ assert((insCodesRM[ins] != BAD_CODE));
+
+ return insCodesRM[ins];
+}
+
+// clang-format off
+const static
+size_t insCodesMI[] =
+{
+ #define INST0(id, nm, fp, um, rf, wf, mr )
+ #define INST1(id, nm, fp, um, rf, wf, mr )
+ #define INST2(id, nm, fp, um, rf, wf, mr, mi ) mi,
+ #define INST3(id, nm, fp, um, rf, wf, mr, mi, rm ) mi,
+ #define INST4(id, nm, fp, um, rf, wf, mr, mi, rm, a4 ) mi,
+ #define INST5(id, nm, fp, um, rf, wf, mr, mi, rm, a4, rr) mi,
+ #include "instrs.h"
+ #undef INST0
+ #undef INST1
+ #undef INST2
+ #undef INST3
+ #undef INST4
+ #undef INST5
+};
+// clang-format on
+
+// Returns true iff the give CPU instruction has an MI encoding.
+inline bool hasCodeMI(instruction ins)
+{
+ assert((unsigned)ins < sizeof(insCodesMI) / sizeof(insCodesMI[0]));
+ return ((insCodesMI[ins] != BAD_CODE));
+}
+
+/*****************************************************************************
+ *
+ * Returns the "[r/m], 32-bit icon" encoding of the given CPU instruction.
+ */
+
+inline size_t insCodeMI(instruction ins)
+{
+ assert((unsigned)ins < sizeof(insCodesMI) / sizeof(insCodesMI[0]));
+ assert((insCodesMI[ins] != BAD_CODE));
+
+ return insCodesMI[ins];
+}
+
+// clang-format off
+const static
size_t insCodesMR[] =
{
#define INST0(id, nm, fp, um, rf, wf, mr )
@@ -1108,6 +1128,32 @@ inline size_t insCodeMR(instruction ins)
return insCodesMR[ins];
}
+// Return true if the instruction uses the SSE38 or SSE3A macro in instrsXArch.h.
+bool emitter::EncodedBySSE38orSSE3A(instruction ins)
+{
+ const size_t SSE38 = 0x0F660038;
+ const size_t SSE3A = 0x0F66003A;
+ const size_t MASK = 0xFFFF00FF;
+
+ size_t insCode = 0;
+
+ if (hasCodeRM(ins))
+ {
+ insCode = insCodeRM(ins);
+ }
+ else if (hasCodeMI(ins))
+ {
+ insCode = insCodeMI(ins);
+ }
+ else if (hasCodeMR(ins))
+ {
+ insCode = insCodeMR(ins);
+ }
+
+ insCode &= MASK;
+ return insCode == SSE38 || insCode == SSE3A;
+}
+
/*****************************************************************************
*
* Returns an encoding for the specified register to be used in the bit0-2
@@ -1622,7 +1668,7 @@ inline UNATIVE_OFFSET emitter::emitInsSizeSV(code_t code, int var, int dsp)
if (EBPbased)
{
-#if defined(_TARGET_AMD64_) && !defined(PLATFORM_UNIX)
+#if defined(_TARGET_AMD64_) && !defined(UNIX_AMD64_ABI)
// If localloc is not used, then ebp chaining is done and hence
// offset of locals will be at negative offsets, Otherwise offsets
// will be positive. In future, when RBP gets positioned in the
@@ -1756,13 +1802,11 @@ inline UNATIVE_OFFSET emitter::emitInsSizeSV(instrDesc* id, int var, int dsp, in
valSize = sizeof(int);
}
-#ifdef RELOC_SUPPORT
if (id->idIsCnsReloc())
{
valInByte = false; // relocs can't be placed in a byte
assert(valSize == sizeof(int));
}
-#endif
if (valInByte)
{
@@ -1838,13 +1882,11 @@ UNATIVE_OFFSET emitter::emitInsSizeAM(instrDesc* id, code_t code)
break;
}
-#ifdef RELOC_SUPPORT
if (id->idIsDspReloc())
{
dspInByte = false; // relocs can't be placed in a byte
dspIsZero = false; // relocs won't always be zero
}
-#endif
if (code & 0xFF000000)
{
@@ -2031,13 +2073,11 @@ inline UNATIVE_OFFSET emitter::emitInsSizeAM(instrDesc* id, code_t code, int val
valSize = sizeof(INT32);
}
-#ifdef RELOC_SUPPORT
if (id->idIsCnsReloc())
{
valInByte = false; // relocs can't be placed in a byte
assert(valSize == sizeof(INT32));
}
-#endif
if (valInByte)
{
@@ -2079,13 +2119,11 @@ inline UNATIVE_OFFSET emitter::emitInsSizeCV(instrDesc* id, code_t code, int val
valSize = sizeof(INT32);
#endif // !_TARGET_AMD64_
-#ifdef RELOC_SUPPORT
if (id->idIsCnsReloc())
{
valInByte = false; // relocs can't be placed in a byte
assert(valSize == sizeof(INT32));
}
-#endif
if (valInByte)
{
@@ -2315,11 +2353,8 @@ void emitter::emitIns(instruction ins)
}
#ifndef LEGACY_BACKEND
- // Account for 2-byte VEX prefix in case of vzeroupper
- if (ins == INS_vzeroupper)
- {
- sz += 2;
- }
+ // vzeroupper includes its 2-byte VEX prefix in its MR code.
+ assert((ins != INS_vzeroupper) || (sz == 3));
#endif
insFormat fmt = IF_NONE;
@@ -3623,13 +3658,11 @@ void emitter::emitIns_IJ(emitAttr attr, regNumber reg, unsigned base)
void emitter::emitIns_C(instruction ins, emitAttr attr, CORINFO_FIELD_HANDLE fldHnd, int offs)
{
-#if RELOC_SUPPORT
// Static always need relocs
if (!jitStaticFldIsGlobAddr(fldHnd))
{
attr = EA_SET_FLG(attr, EA_DSP_RELOC_FLG);
}
-#endif
UNATIVE_OFFSET sz;
instrDesc* id;
@@ -3791,13 +3824,11 @@ void emitter::emitIns_R_R_R(instruction ins, emitAttr attr, regNumber targetReg,
*/
void emitter::emitIns_R_C(instruction ins, emitAttr attr, regNumber reg, CORINFO_FIELD_HANDLE fldHnd, int offs)
{
-#if RELOC_SUPPORT
// Static always need relocs
if (!jitStaticFldIsGlobAddr(fldHnd))
{
attr = EA_SET_FLG(attr, EA_DSP_RELOC_FLG);
}
-#endif
emitAttr size = EA_SIZE(attr);
@@ -3876,13 +3907,11 @@ void emitter::emitIns_R_C(instruction ins, emitAttr attr, regNumber reg, CORINFO
void emitter::emitIns_C_R(instruction ins, emitAttr attr, CORINFO_FIELD_HANDLE fldHnd, regNumber reg, int offs)
{
-#if RELOC_SUPPORT
// Static always need relocs
if (!jitStaticFldIsGlobAddr(fldHnd))
{
attr = EA_SET_FLG(attr, EA_DSP_RELOC_FLG);
}
-#endif
emitAttr size = EA_SIZE(attr);
@@ -3951,13 +3980,11 @@ void emitter::emitIns_C_R(instruction ins, emitAttr attr, CORINFO_FIELD_HANDLE f
void emitter::emitIns_C_I(instruction ins, emitAttr attr, CORINFO_FIELD_HANDLE fldHnd, int offs, int val)
{
-#if RELOC_SUPPORT
// Static always need relocs
if (!jitStaticFldIsGlobAddr(fldHnd))
{
attr = EA_SET_FLG(attr, EA_DSP_RELOC_FLG);
}
-#endif
insFormat fmt;
@@ -4039,7 +4066,6 @@ void emitter::emitIns_J_S(instruction ins, emitAttr attr, BasicBlock* dst, int v
emitTotalIGjmps++;
#endif
-#if RELOC_SUPPORT
#ifndef _TARGET_AMD64_
// Storing the address of a basicBlock will need a reloc
// as the instruction uses the absolute address,
@@ -4052,7 +4078,6 @@ void emitter::emitIns_J_S(instruction ins, emitAttr attr, BasicBlock* dst, int v
{
id->idSetIsDspReloc();
}
-#endif // RELOC_SUPPORT
id->idCodeSize(sz);
@@ -4984,7 +5009,6 @@ void emitter::emitIns_J(instruction ins, BasicBlock* dst, int instrCount /* = 0
}
else if (ins == INS_push || ins == INS_push_hide)
{
-#if RELOC_SUPPORT
// Pushing the address of a basicBlock will need a reloc
// as the instruction uses the absolute address,
// not a relative address
@@ -4992,7 +5016,6 @@ void emitter::emitIns_J(instruction ins, BasicBlock* dst, int instrCount /* = 0
{
id->idSetIsDspReloc();
}
-#endif
sz = PUSH_INST_SIZE;
}
else
@@ -5097,7 +5120,10 @@ void emitter::emitAdjustStackDepthPushPop(instruction ins)
emitCurStackLvl += emitCntStackDepth;
if (emitMaxStackDepth < emitCurStackLvl)
+ {
+ JITDUMP("Upping emitMaxStackDepth from %d to %d\n", emitMaxStackDepth, emitCurStackLvl);
emitMaxStackDepth = emitCurStackLvl;
+ }
}
else if (ins == INS_pop)
{
@@ -5133,7 +5159,10 @@ void emitter::emitAdjustStackDepth(instruction ins, ssize_t val)
emitCurStackLvl = newStackLvl.Value();
if (emitMaxStackDepth < emitCurStackLvl)
+ {
+ JITDUMP("Upping emitMaxStackDepth from %d to %d\n", emitMaxStackDepth, emitCurStackLvl);
emitMaxStackDepth = emitCurStackLvl;
+ }
}
else if (ins == INS_add)
{
@@ -5167,22 +5196,25 @@ void emitter::emitAdjustStackDepth(instruction ins, ssize_t val)
*
*/
+// clang-format off
void emitter::emitIns_Call(EmitCallType callType,
CORINFO_METHOD_HANDLE methHnd,
INDEBUG_LDISASM_COMMA(CORINFO_SIG_INFO* sigInfo) // used to report call sites to the EE
- void* addr,
- ssize_t argSize,
- emitAttr retSize MULTIREG_HAS_SECOND_GC_RET_ONLY_ARG(emitAttr secondRetSize),
- VARSET_VALARG_TP ptrVars,
- regMaskTP gcrefRegs,
- regMaskTP byrefRegs,
- IL_OFFSETX ilOffset, // = BAD_IL_OFFSET
- regNumber ireg, // = REG_NA
- regNumber xreg, // = REG_NA
- unsigned xmul, // = 0
- ssize_t disp, // = 0
- bool isJump, // = false
- bool isNoGC) // = false
+ void* addr,
+ ssize_t argSize,
+ emitAttr retSize
+ MULTIREG_HAS_SECOND_GC_RET_ONLY_ARG(emitAttr secondRetSize),
+ VARSET_VALARG_TP ptrVars,
+ regMaskTP gcrefRegs,
+ regMaskTP byrefRegs,
+ IL_OFFSETX ilOffset, // = BAD_IL_OFFSET
+ regNumber ireg, // = REG_NA
+ regNumber xreg, // = REG_NA
+ unsigned xmul, // = 0
+ ssize_t disp, // = 0
+ bool isJump, // = false
+ bool isNoGC) // = false
+// clang-format on
{
/* Sanity check the arguments depending on callType */
@@ -5480,7 +5512,6 @@ void emitter::emitIns_Call(EmitCallType callType,
id->idAddr()->iiaAddr = (BYTE*)addr;
sz = 6;
-#if RELOC_SUPPORT
// Since this is an indirect call through a pointer and we don't
// currently pass in emitAttr into this function, we query codegen
// whether addr needs a reloc.
@@ -5498,7 +5529,6 @@ void emitter::emitIns_Call(EmitCallType callType,
sz++;
}
#endif //_TARGET_AMD64_
-#endif // RELOC_SUPPORT
}
else
{
@@ -5518,13 +5548,11 @@ void emitter::emitIns_Call(EmitCallType callType,
id->idSetIsCallAddr();
}
-#if RELOC_SUPPORT
// Direct call to a method and no addr indirection is needed.
if (codeGen->genCodeAddrNeedsReloc((size_t)addr))
{
id->idSetIsDspReloc();
}
-#endif
}
#ifdef DEBUG
@@ -5979,12 +6007,10 @@ void emitter::emitDispClsVar(CORINFO_FIELD_HANDLE fldHnd, ssize_t offs, bool rel
doffs = Compiler::eeGetJitDataOffs(fldHnd);
-#ifdef RELOC_SUPPORT
if (reloc)
{
printf("reloc ");
}
-#endif
if (doffs >= 0)
{
@@ -6200,12 +6226,10 @@ void emitter::emitDispAddrMode(instrDesc* id, bool noDetail)
if (jdsc)
{
-#ifdef RELOC_SUPPORT
if (id->idIsDspReloc())
{
printf("reloc ");
}
-#endif
printf("J_M%03u_DS%02u", Compiler::s_compMethodsCount, id->idDebugOnlyInfo()->idMemCookie);
}
@@ -6246,7 +6270,6 @@ void emitter::emitDispAddrMode(instrDesc* id, bool noDetail)
nsep = true;
}
-#ifdef RELOC_SUPPORT
if ((id->idIsDspReloc()) && (id->idIns() != INS_i_jmp))
{
if (nsep)
@@ -6256,7 +6279,6 @@ void emitter::emitDispAddrMode(instrDesc* id, bool noDetail)
emitDispReloc(disp);
}
else
-#endif
{
// Munge any pointers if we want diff-able disassembly
if (emitComp->opts.disDiffable)
@@ -6463,11 +6485,8 @@ void emitter::emitDispIns(
printf("IN%04x: ", idNum);
}
-#ifdef RELOC_SUPPORT
#define ID_INFO_DSP_RELOC ((bool)(id->idIsDspReloc()))
-#else
-#define ID_INFO_DSP_RELOC false
-#endif
+
/* Display a constant value if the instruction references one */
if (!isNew)
@@ -6684,13 +6703,11 @@ void emitter::emitDispIns(
// no 8-byte immediates allowed here!
assert((val >= 0xFFFFFFFF80000000LL) && (val <= 0x000000007FFFFFFFLL));
#endif
-#ifdef RELOC_SUPPORT
if (id->idIsCnsReloc())
{
emitDispReloc(val);
}
else
-#endif
{
PRINT_CONSTANT:
// Munge any pointers if we want diff-able disassembly
@@ -6812,13 +6829,11 @@ void emitter::emitDispIns(
else
{
printf(", ");
-#ifdef RELOC_SUPPORT
if (cnsVal.cnsReloc)
{
emitDispReloc(val);
}
else
-#endif
{
goto PRINT_CONSTANT;
}
@@ -6893,13 +6908,11 @@ void emitter::emitDispIns(
else
{
printf(", ");
-#ifdef RELOC_SUPPORT
if (cnsVal.cnsReloc)
{
emitDispReloc(val);
}
else
-#endif
{
goto PRINT_CONSTANT;
}
@@ -6999,13 +7012,11 @@ void emitter::emitDispIns(
assert((val >= 0xFFFFFFFF80000000LL) && (val <= 0x000000007FFFFFFFLL));
#endif
printf(", ");
-#ifdef RELOC_SUPPORT
if (id->idIsCnsReloc())
{
emitDispReloc(val);
}
else
-#endif
{
goto PRINT_CONSTANT;
}
@@ -7073,14 +7084,11 @@ void emitter::emitDispIns(
// no 8-byte immediates allowed here!
assert((val >= 0xFFFFFFFF80000000LL) && (val <= 0x000000007FFFFFFFLL));
#endif
-#ifdef RELOC_SUPPORT
if (cnsVal.cnsReloc)
{
emitDispReloc(val);
}
- else
-#endif
- if (id->idInsFmt() == IF_MRW_SHF)
+ else if (id->idInsFmt() == IF_MRW_SHF)
{
emitDispShift(ins, (BYTE)val);
}
@@ -7125,13 +7133,11 @@ void emitter::emitDispIns(
case IF_RRW_CNS:
printf("%s, ", emitRegName(id->idReg1(), attr));
val = emitGetInsSC(id);
-#ifdef RELOC_SUPPORT
if (id->idIsCnsReloc())
{
emitDispReloc(val);
}
else
-#endif
{
goto PRINT_CONSTANT;
}
@@ -7477,11 +7483,7 @@ BYTE* emitter::emitOutputAM(BYTE* dst, instrDesc* id, code_t code, CnsVal* addc)
ssize_t cval = addc->cnsVal;
// Does the constant fit in a byte?
- if ((signed char)cval == cval &&
-#ifdef RELOC_SUPPORT
- addc->cnsReloc == false &&
-#endif
- ins != INS_mov && ins != INS_test)
+ if ((signed char)cval == cval && addc->cnsReloc == false && ins != INS_mov && ins != INS_test)
{
if (id->idInsFmt() != IF_ARW_SHF)
{
@@ -7626,12 +7628,10 @@ GOT_DSP:
dspInByte = ((signed char)dsp == (ssize_t)dsp);
dspIsZero = (dsp == 0);
-#ifdef RELOC_SUPPORT
if (id->idIsDspReloc())
{
dspInByte = false; // relocs can't be placed in a byte
}
-#endif
// Is there a [scaled] index component?
if (rgx == REG_NA)
@@ -7725,12 +7725,10 @@ GOT_DSP:
dst += emitOutputWord(dst, code | 0x8500);
dst += emitOutputLong(dst, dsp);
-#ifdef RELOC_SUPPORT
if (id->idIsDspReloc())
{
emitRecordRelocation((void*)(dst - sizeof(INT32)), (void*)dsp, IMAGE_REL_BASED_HIGHLOW);
}
-#endif
}
break;
@@ -7765,12 +7763,10 @@ GOT_DSP:
dst += emitOutputWord(dst, code | 0x8400);
dst += emitOutputByte(dst, 0x24);
dst += emitOutputLong(dst, dsp);
-#ifdef RELOC_SUPPORT
if (id->idIsDspReloc())
{
emitRecordRelocation((void*)(dst - sizeof(INT32)), (void*)dsp, IMAGE_REL_BASED_HIGHLOW);
}
-#endif
}
break;
@@ -7796,12 +7792,10 @@ GOT_DSP:
{
dst += emitOutputWord(dst, code | 0x8000);
dst += emitOutputLong(dst, dsp);
-#ifdef RELOC_SUPPORT
if (id->idIsDspReloc())
{
emitRecordRelocation((void*)(dst - sizeof(INT32)), (void*)dsp, IMAGE_REL_BASED_HIGHLOW);
}
-#endif
}
}
@@ -7846,12 +7840,10 @@ GOT_DSP:
dst += emitOutputWord(dst, code | 0x8400);
dst += emitOutputByte(dst, regByte);
dst += emitOutputLong(dst, dsp);
-#ifdef RELOC_SUPPORT
if (id->idIsDspReloc())
{
emitRecordRelocation((void*)(dst - sizeof(INT32)), (void*)dsp, IMAGE_REL_BASED_HIGHLOW);
}
-#endif
}
}
}
@@ -7871,12 +7863,10 @@ GOT_DSP:
}
dst += emitOutputLong(dst, dsp);
-#ifdef RELOC_SUPPORT
if (id->idIsDspReloc())
{
emitRecordRelocation((void*)(dst - sizeof(INT32)), (void*)dsp, IMAGE_REL_BASED_HIGHLOW);
}
-#endif
}
}
else
@@ -7904,12 +7894,10 @@ GOT_DSP:
dst += emitOutputWord(dst, code | 0x8400);
dst += emitOutputByte(dst, regByte);
dst += emitOutputLong(dst, dsp);
-#ifdef RELOC_SUPPORT
if (id->idIsDspReloc())
{
emitRecordRelocation((void*)(dst - sizeof(INT32)), (void*)dsp, IMAGE_REL_BASED_HIGHLOW);
}
-#endif
}
}
}
@@ -7943,13 +7931,11 @@ GOT_DSP:
assert(!"unexpected operand size");
}
-#ifdef RELOC_SUPPORT
if (addc->cnsReloc)
{
emitRecordRelocation((void*)(dst - sizeof(INT32)), (void*)(size_t)cval, IMAGE_REL_BASED_HIGHLOW);
assert(opsz == 4);
}
-#endif
}
DONE:
@@ -8099,11 +8085,7 @@ BYTE* emitter::emitOutputSV(BYTE* dst, instrDesc* id, code_t code, CnsVal* addc)
ssize_t cval = addc->cnsVal;
// Does the constant fit in a byte?
- if ((signed char)cval == cval &&
-#ifdef RELOC_SUPPORT
- addc->cnsReloc == false &&
-#endif
- ins != INS_mov && ins != INS_test)
+ if ((signed char)cval == cval && addc->cnsReloc == false && ins != INS_mov && ins != INS_test)
{
if (id->idInsFmt() != IF_SRW_SHF)
{
@@ -8238,10 +8220,8 @@ BYTE* emitter::emitOutputSV(BYTE* dst, instrDesc* id, code_t code, CnsVal* addc)
dspInByte = ((signed char)dsp == (int)dsp);
dspIsZero = (dsp == 0);
-#ifdef RELOC_SUPPORT
// for stack varaibles the dsp should never be a reloc
assert(id->idIsDspReloc() == 0);
-#endif
if (EBPbased)
{
@@ -8361,13 +8341,11 @@ BYTE* emitter::emitOutputSV(BYTE* dst, instrDesc* id, code_t code, CnsVal* addc)
assert(!"unexpected operand size");
}
-#ifdef RELOC_SUPPORT
if (addc->cnsReloc)
{
emitRecordRelocation((void*)(dst - sizeof(INT32)), (void*)(size_t)cval, IMAGE_REL_BASED_HIGHLOW);
assert(opsz == 4);
}
-#endif
}
// Does this instruction operate on a GC ref value?
@@ -8510,11 +8488,7 @@ BYTE* emitter::emitOutputCV(BYTE* dst, instrDesc* id, code_t code, CnsVal* addc)
{
ssize_t cval = addc->cnsVal;
// Does the constant fit in a byte?
- if ((signed char)cval == cval &&
-#ifdef RELOC_SUPPORT
- addc->cnsReloc == false &&
-#endif
- ins != INS_mov && ins != INS_test)
+ if ((signed char)cval == cval && addc->cnsReloc == false && ins != INS_mov && ins != INS_test)
{
if (id->idInsFmt() != IF_MRW_SHF)
{
@@ -8756,12 +8730,10 @@ BYTE* emitter::emitOutputCV(BYTE* dst, instrDesc* id, code_t code, CnsVal* addc)
dst += emitOutputLong(dst, (int)target);
#endif //_TARGET_X86_
-#ifdef RELOC_SUPPORT
if (id->idIsDspReloc())
{
emitRecordRelocation((void*)(dst - sizeof(int)), target, IMAGE_REL_BASED_DISP32, 0, addlDelta);
}
-#endif
}
else
{
@@ -8774,12 +8746,10 @@ BYTE* emitter::emitOutputCV(BYTE* dst, instrDesc* id, code_t code, CnsVal* addc)
dst += emitOutputSizeT(dst, (ssize_t)target);
-#ifdef RELOC_SUPPORT
if (id->idIsDspReloc())
{
emitRecordRelocation((void*)(dst - sizeof(void*)), target, IMAGE_REL_BASED_MOFFSET);
}
-#endif
#endif //_TARGET_X86_
}
@@ -8811,13 +8781,11 @@ BYTE* emitter::emitOutputCV(BYTE* dst, instrDesc* id, code_t code, CnsVal* addc)
default:
assert(!"unexpected operand size");
}
-#ifdef RELOC_SUPPORT
if (addc->cnsReloc)
{
emitRecordRelocation((void*)(dst - sizeof(INT32)), (void*)(size_t)cval, IMAGE_REL_BASED_HIGHLOW);
assert(opsz == 4);
}
-#endif
}
// Does this instruction operate on a GC ref value?
@@ -9539,12 +9507,10 @@ BYTE* emitter::emitOutputRI(BYTE* dst, instrDesc* id)
ssize_t val = emitGetInsSC(id);
bool valInByte = ((signed char)val == val) && (ins != INS_mov) && (ins != INS_test);
-#ifdef RELOC_SUPPORT
if (id->idIsCnsReloc())
{
valInByte = false; // relocs can't be placed in a byte
}
-#endif
noway_assert(emitVerifyEncodable(ins, size, reg));
@@ -9632,12 +9598,10 @@ BYTE* emitter::emitOutputRI(BYTE* dst, instrDesc* id)
}
#endif
-#ifdef RELOC_SUPPORT
if (id->idIsCnsReloc())
{
emitRecordRelocation((void*)(dst - (unsigned)EA_SIZE(size)), (void*)(size_t)val, IMAGE_REL_BASED_MOFFSET);
}
-#endif
goto DONE;
}
@@ -9794,13 +9758,11 @@ BYTE* emitter::emitOutputRI(BYTE* dst, instrDesc* id)
break;
}
-#ifdef RELOC_SUPPORT
if (id->idIsCnsReloc())
{
emitRecordRelocation((void*)(dst - sizeof(INT32)), (void*)(size_t)val, IMAGE_REL_BASED_HIGHLOW);
assert(size == EA_4BYTE);
}
-#endif
}
DONE:
@@ -9909,7 +9871,6 @@ BYTE* emitter::emitOutputIV(BYTE* dst, instrDesc* id)
noway_assert(size < EA_8BYTE || ((int)val == val && !id->idIsCnsReloc()));
#endif
-#ifdef RELOC_SUPPORT
if (id->idIsCnsReloc())
{
valInByte = false; // relocs can't be placed in a byte
@@ -9917,7 +9878,6 @@ BYTE* emitter::emitOutputIV(BYTE* dst, instrDesc* id)
// Of these instructions only the push instruction can have reloc
assert(ins == INS_push || ins == INS_push_hide);
}
-#endif
switch (ins)
{
@@ -9959,12 +9919,10 @@ BYTE* emitter::emitOutputIV(BYTE* dst, instrDesc* id)
dst += emitOutputByte(dst, code);
dst += emitOutputLong(dst, val);
-#ifdef RELOC_SUPPORT
if (id->idIsCnsReloc())
{
emitRecordRelocation((void*)(dst - sizeof(INT32)), (void*)(size_t)val, IMAGE_REL_BASED_HIGHLOW);
}
-#endif
}
// Did we push a GC ref value?
@@ -10551,12 +10509,10 @@ size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp)
dst += emitOutputLong(dst, offset);
-#ifdef RELOC_SUPPORT
if (id->idIsDspReloc())
{
emitRecordRelocation((void*)(dst - sizeof(INT32)), addr, IMAGE_REL_BASED_REL32);
}
-#endif
DONE_CALL:
generated by cgit v1.2.3 (git 2.25.1) at 2024-04-20 06:45:13 +0000