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| author | Carol Eidt <carol.eidt@microsoft.com> | 2019-04-18 16:05:34 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-04-18 16:05:34 -0700 |
| commit | 7e8c5b66c1126b56e28874d634465825f2b07c50 (patch) | |
| tree | bf5379fbc5fa27cc52818793f5da440f5b7482c6 /src | |
| parent | 1a2bc6c63ebeff1452ac9ae05b2b0eda058062fa (diff) | |
| download | coreclr-7e8c5b66c1126b56e28874d634465825f2b07c50.tar.gz coreclr-7e8c5b66c1126b56e28874d634465825f2b07c50.tar.bz2 coreclr-7e8c5b66c1126b56e28874d634465825f2b07c50.zip | |
Allow UpperVector Save and Restore without base type (#24080)
Fixes an issue with crossgen on Arm64/linux
Diffstat (limited to 'src')
| -rw-r--r-- | src/jit/codegenarm64.cpp | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/src/jit/codegenarm64.cpp b/src/jit/codegenarm64.cpp index efbb59007c..da678dc17b 100644 --- a/src/jit/codegenarm64.cpp +++ b/src/jit/codegenarm64.cpp @@ -3875,7 +3875,14 @@ void CodeGen::genSIMDIntrinsic(GenTreeSIMD* simdNode) simdNode->gtSIMDBaseType != TYP_SHORT && simdNode->gtSIMDBaseType != TYP_BYTE && simdNode->gtSIMDBaseType != TYP_UINT && simdNode->gtSIMDBaseType != TYP_ULONG) { - noway_assert(!"SIMD intrinsic with unsupported base type."); + // We don't need a base type for the Upper Save & Restore intrinsics, and we may find + // these implemented over lclVars created by CSE without full handle information (and + // therefore potentially without a base type). + if ((simdNode->gtSIMDIntrinsicID != SIMDIntrinsicUpperSave) && + (simdNode->gtSIMDIntrinsicID != SIMDIntrinsicUpperRestore)) + { + noway_assert(!"SIMD intrinsic with unsupported base type."); + } } switch (simdNode->gtSIMDIntrinsicID) |