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author | Carol Eidt <carol.eidt@microsoft.com> | 2019-03-29 16:35:09 -0700 |
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committer | GitHub <noreply@github.com> | 2019-03-29 16:35:09 -0700 |
commit | 1df87c785e0e43392abf4bcba56e2bf4d9249fd4 (patch) | |
tree | 9e8838acba72027ac276ab36f27439ed0b0f1223 /src | |
parent | 8c7d91177742e150b91f11cf37da84b8f80f6620 (diff) | |
download | coreclr-1df87c785e0e43392abf4bcba56e2bf4d9249fd4.tar.gz coreclr-1df87c785e0e43392abf4bcba56e2bf4d9249fd4.tar.bz2 coreclr-1df87c785e0e43392abf4bcba56e2bf4d9249fd4.zip |
Fix HW intrinsic containment bugs (#23558)
* Fix HW intrinsic containment bugs
For the Fma case (#23430), fix the handling of contained 3-operand HW intrinsic nodes.
For the Bmi case (#23534), fix a bad assert placement, and re-enable the Bmi tests.
Fix #23530
Fix #23534
* Add guard for Fma test
Diffstat (limited to 'src')
-rw-r--r-- | src/jit/hwintrinsiccodegenxarch.cpp | 46 |
1 files changed, 27 insertions, 19 deletions
diff --git a/src/jit/hwintrinsiccodegenxarch.cpp b/src/jit/hwintrinsiccodegenxarch.cpp index 4d63bef6ef..37d551ff1f 100644 --- a/src/jit/hwintrinsiccodegenxarch.cpp +++ b/src/jit/hwintrinsiccodegenxarch.cpp @@ -1045,39 +1045,47 @@ void CodeGen::genHWIntrinsic_R_R_R_RM( regSet.tmpRlsTemp(tmpDsc); } - else if (op3->OperIsHWIntrinsic()) + else if (op3->isIndir() || op3->OperIsHWIntrinsic()) { - emit->emitIns_SIMD_R_R_R_AR(ins, attr, targetReg, op1Reg, op2Reg, op3->gtGetOp1()->gtRegNum); - return; - } - else if (op3->isIndir()) - { - GenTreeIndir* memIndir = op3->AsIndir(); - GenTree* memBase = memIndir->gtOp1; + GenTree* addr; + GenTreeIndir* memIndir = nullptr; + if (op3->isIndir()) + { + memIndir = op3->AsIndir(); + addr = memIndir->Addr(); + } + else + { + assert(op3->AsHWIntrinsic()->OperIsMemoryLoad()); + assert(HWIntrinsicInfo::lookupNumArgs(op3->AsHWIntrinsic()) == 1); + addr = op3->gtGetOp1(); + } - switch (memBase->OperGet()) + switch (addr->OperGet()) { case GT_LCL_VAR_ADDR: { - varNum = memBase->AsLclVarCommon()->GetLclNum(); + varNum = addr->AsLclVarCommon()->GetLclNum(); offset = 0; - - // Ensure that all the GenTreeIndir values are set to their defaults. - assert(!memIndir->HasIndex()); - assert(memIndir->Scale() == 1); - assert(memIndir->Offset() == 0); - break; } case GT_CLS_VAR_ADDR: { - emit->emitIns_SIMD_R_R_R_C(ins, attr, targetReg, op1Reg, op2Reg, memBase->gtClsVar.gtClsVarHnd, 0); + emit->emitIns_SIMD_R_R_R_C(ins, attr, targetReg, op1Reg, op2Reg, addr->gtClsVar.gtClsVarHnd, 0); return; } default: { + if (memIndir == nullptr) + { + // This is the HW intrinsic load case. + // Until we improve the handling of addressing modes in the emitter, we'll create a + // temporary GT_IND to generate code with. + GenTreeIndir load = indirForm(op3->TypeGet(), addr); + memIndir = &load; + } emit->emitIns_SIMD_R_R_R_A(ins, attr, targetReg, op1Reg, op2Reg, memIndir); return; } @@ -2132,8 +2140,6 @@ void CodeGen::genBMI1OrBMI2Intrinsic(GenTreeHWIntrinsic* node) case NI_BMI2_MultiplyNoFlags: case NI_BMI2_X64_MultiplyNoFlags: { - // These do not support containment - assert(!op2->isContained()); int numArgs = HWIntrinsicInfo::lookupNumArgs(node); assert(numArgs == 2 || numArgs == 3); @@ -2168,6 +2174,8 @@ void CodeGen::genBMI1OrBMI2Intrinsic(GenTreeHWIntrinsic* node) assert(lowReg != targetReg); } + // These do not support containment + assert(!op2->isContained()); emitAttr attr = emitTypeSize(targetType); // mov the first operand into implicit source operand EDX/RDX if (op1Reg != REG_EDX) |