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author | Steve MacLean <Steve.MacLean@microsoft.com> | 2019-07-18 11:39:01 -0400 |
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committer | Steve MacLean <Steve.MacLean@Microsoft.com> | 2019-07-18 15:04:14 -0400 |
commit | 3f1804543d5021ea0cae4d46090e3a1ece96a7ba (patch) | |
tree | 7bac32c5f9b491b4cddd6b7c63aa2885a3cc4b8f /src | |
parent | 404e72adc3e721ef67b62c26a26c3e0112e67ed3 (diff) | |
download | coreclr-3f1804543d5021ea0cae4d46090e3a1ece96a7ba.tar.gz coreclr-3f1804543d5021ea0cae4d46090e3a1ece96a7ba.tar.bz2 coreclr-3f1804543d5021ea0cae4d46090e3a1ece96a7ba.zip |
Arm64 : Fix ldr Dt/St emulation (#25729)
Diffstat (limited to 'src')
-rw-r--r-- | src/debug/ee/arm64/arm64walker.cpp | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/src/debug/ee/arm64/arm64walker.cpp b/src/debug/ee/arm64/arm64walker.cpp index b38297b3ec..398d326e8a 100644 --- a/src/debug/ee/arm64/arm64walker.cpp +++ b/src/debug/ee/arm64/arm64walker.cpp @@ -200,12 +200,15 @@ BYTE* NativeWalker::SetupOrSimulateInstructionForPatchSkip(T_CONTEXT * context, switch (opc) { case 0: //4byte data into St - RegContents = 0xFFFFFFFF & RegContents; //zero the upper 32bit - SetReg(context, RegNum, RegContents); + SimdRegContents.Low = 0xFFFFFFFF & RegContents; //zero the upper 32bit + SimdRegContents.High = 0; + SetSimdReg(context, RegNum, SimdRegContents); + break; case 1: //8byte data into Dt - SetReg(context, RegNum, RegContents); + SimdRegContents.Low = RegContents; + SimdRegContents.High = 0; + SetSimdReg(context, RegNum, SimdRegContents); break; - case 2: //SIMD 16 byte data SimdRegContents = GetSimdMem(ip); SetSimdReg(context, RegNum, SimdRegContents); |