diff options
author | Bruce Forstall <brucefo@microsoft.com> | 2018-01-19 17:18:49 -0800 |
---|---|---|
committer | Bruce Forstall <brucefo@microsoft.com> | 2018-01-19 17:18:49 -0800 |
commit | 79a08ff79ff73fbfb5009236ee9f3201d2226bb4 (patch) | |
tree | b3146a193b65437986218e82fe8efb03d2fd108a /src | |
parent | 9afce33defce540c810f3e8806568fb4c3b37732 (diff) | |
download | coreclr-79a08ff79ff73fbfb5009236ee9f3201d2226bb4.tar.gz coreclr-79a08ff79ff73fbfb5009236ee9f3201d2226bb4.tar.bz2 coreclr-79a08ff79ff73fbfb5009236ee9f3201d2226bb4.zip |
Fix desktop build
1. Fix `LEGACY_BACKEND`
2. `#if FEATURE_HW_INTRINSICS` => `#ifdef FEATURE_HW_INTRINSICS`
[tfs-changeset: 1686599]
Diffstat (limited to 'src')
-rw-r--r-- | src/jit/codegenlinear.h | 4 | ||||
-rw-r--r-- | src/jit/codegenxarch.cpp | 2 | ||||
-rw-r--r-- | src/jit/compiler.cpp | 2 | ||||
-rw-r--r-- | src/jit/compiler.h | 8 | ||||
-rw-r--r-- | src/jit/compiler.hpp | 2 | ||||
-rw-r--r-- | src/jit/emitxarch.cpp | 22 | ||||
-rw-r--r-- | src/jit/emitxarch.h | 22 | ||||
-rw-r--r-- | src/jit/gentree.cpp | 16 | ||||
-rw-r--r-- | src/jit/gentree.h | 8 | ||||
-rw-r--r-- | src/jit/gtlist.h | 2 | ||||
-rw-r--r-- | src/jit/gtstructs.h | 2 | ||||
-rw-r--r-- | src/jit/importer.cpp | 10 | ||||
-rw-r--r-- | src/jit/lsra.h | 2 | ||||
-rw-r--r-- | src/jit/lsraxarch.cpp | 4 | ||||
-rw-r--r-- | src/jit/simd.cpp | 2 | ||||
-rw-r--r-- | src/jit/valuenum.cpp | 2 |
16 files changed, 60 insertions, 50 deletions
diff --git a/src/jit/codegenlinear.h b/src/jit/codegenlinear.h index 6321e0c913..4263b2cc40 100644 --- a/src/jit/codegenlinear.h +++ b/src/jit/codegenlinear.h @@ -114,7 +114,7 @@ void genPutArgStkSIMD12(GenTree* treeNode); #endif // _TARGET_X86_ #endif // FEATURE_SIMD -#if FEATURE_HW_INTRINSICS && defined(_TARGET_XARCH_) +#if defined(FEATURE_HW_INTRINSICS) && defined(_TARGET_XARCH_) void genHWIntrinsic(GenTreeHWIntrinsic* node); void genHWIntrinsic_R_R_RM(GenTreeHWIntrinsic* node, instruction ins); void genHWIntrinsic_R_R_RM_I(GenTreeHWIntrinsic* node, instruction ins); @@ -133,7 +133,7 @@ void genFMAIntrinsic(GenTreeHWIntrinsic* node); void genLZCNTIntrinsic(GenTreeHWIntrinsic* node); void genPCLMULQDQIntrinsic(GenTreeHWIntrinsic* node); void genPOPCNTIntrinsic(GenTreeHWIntrinsic* node); -#endif // FEATURE_HW_INTRINSICS +#endif // defined(FEATURE_HW_INTRINSICS) && defined(_TARGET_XARCH_) #if !defined(_TARGET_64BIT_) diff --git a/src/jit/codegenxarch.cpp b/src/jit/codegenxarch.cpp index 1e99da45bd..2f838ce17d 100644 --- a/src/jit/codegenxarch.cpp +++ b/src/jit/codegenxarch.cpp @@ -1860,7 +1860,7 @@ void CodeGen::genCodeForTreeNode(GenTreePtr treeNode) break; #endif // FEATURE_SIMD -#if FEATURE_HW_INTRINSICS +#ifdef FEATURE_HW_INTRINSICS case GT_HWIntrinsic: genHWIntrinsic(treeNode->AsHWIntrinsic()); break; diff --git a/src/jit/compiler.cpp b/src/jit/compiler.cpp index 4661dbc1de..e297faac14 100644 --- a/src/jit/compiler.cpp +++ b/src/jit/compiler.cpp @@ -2116,7 +2116,7 @@ void Compiler::compInit(ArenaAllocator* pAlloc, InlineInfo* inlineInfo) SIMDVector3Handle = nullptr; SIMDVector4Handle = nullptr; SIMDVectorHandle = nullptr; -#if FEATURE_HW_INTRINSICS +#ifdef FEATURE_HW_INTRINSICS #if defined(_TARGET_ARM64_) Vector64FloatHandle = nullptr; Vector64DoubleHandle = nullptr; diff --git a/src/jit/compiler.h b/src/jit/compiler.h index 9cc119a0fd..e92768f3ad 100644 --- a/src/jit/compiler.h +++ b/src/jit/compiler.h @@ -2056,7 +2056,7 @@ public: void SetOpLclRelatedToSIMDIntrinsic(GenTreePtr op); #endif -#if FEATURE_HW_INTRINSICS +#ifdef FEATURE_HW_INTRINSICS GenTreeHWIntrinsic* gtNewSimdHWIntrinsicNode(var_types type, NamedIntrinsic hwIntrinsicID, var_types baseType, @@ -3041,7 +3041,7 @@ protected: bool tailCall); NamedIntrinsic lookupNamedIntrinsic(CORINFO_METHOD_HANDLE method); -#if FEATURE_HW_INTRINSICS +#ifdef FEATURE_HW_INTRINSICS static InstructionSet lookupHWIntrinsicISA(const char* className); static NamedIntrinsic lookupHWIntrinsic(const char* methodName, InstructionSet isa); static InstructionSet isaOfHWIntrinsic(NamedIntrinsic intrinsic); @@ -7479,7 +7479,7 @@ private: CORINFO_CLASS_HANDLE SIMDVector4Handle; CORINFO_CLASS_HANDLE SIMDVectorHandle; -#if FEATURE_HW_INTRINSICS +#ifdef FEATURE_HW_INTRINSICS #if defined(_TARGET_ARM64_) CORINFO_CLASS_HANDLE Vector64FloatHandle; CORINFO_CLASS_HANDLE Vector64DoubleHandle; @@ -7830,7 +7830,7 @@ private: // AVX2: 32-byte Vector<T> and Vector256<T> unsigned int maxSIMDStructBytes() { -#if FEATURE_HW_INTRINSICS && defined(_TARGET_XARCH_) +#if defined(FEATURE_HW_INTRINSICS) && defined(_TARGET_XARCH_) if (compSupports(InstructionSet_AVX)) { return YMM_REGSIZE_BYTES; diff --git a/src/jit/compiler.hpp b/src/jit/compiler.hpp index b1dcde30e1..7e1619ba1f 100644 --- a/src/jit/compiler.hpp +++ b/src/jit/compiler.hpp @@ -4891,7 +4891,7 @@ void GenTree::VisitOperands(TVisitor visitor) return; #endif // FEATURE_SIMD -#if FEATURE_HW_INTRINSICS +#ifdef FEATURE_HW_INTRINSICS case GT_HWIntrinsic: if ((this->AsHWIntrinsic()->gtOp1 != nullptr) && this->AsHWIntrinsic()->gtOp1->OperIsList()) { diff --git a/src/jit/emitxarch.cpp b/src/jit/emitxarch.cpp index 8181e5056d..7354ef9bfd 100644 --- a/src/jit/emitxarch.cpp +++ b/src/jit/emitxarch.cpp @@ -1599,7 +1599,7 @@ bool emitter::emitVerifyEncodable(instruction ins, emitAttr size, regNumber reg1 if ((ins != INS_movsx) && // These three instructions support high register (ins != INS_movzx) // encodings for reg1 -#if FEATURE_HW_INTRINSICS +#ifdef FEATURE_HW_INTRINSICS && (ins != INS_crc32) #endif ) @@ -4274,17 +4274,7 @@ void emitter::emitIns_R_R_S_I( emitCurIGsize += sz; } -#ifdef DEBUG -static bool isAvxBlendv(instruction ins) -{ - return ins == INS_vblendvps || ins == INS_vblendvpd || ins == INS_vpblendvb; -} - -static bool isSse41Blendv(instruction ins) -{ - return ins == INS_blendvps || ins == INS_blendvpd || ins == INS_pblendvb; -} -#endif +#ifndef LEGACY_BACKEND void emitter::emitIns_R_R_R_R( instruction ins, emitAttr attr, regNumber targetReg, regNumber reg1, regNumber reg2, regNumber reg3) @@ -4313,6 +4303,8 @@ void emitter::emitIns_R_R_R_R( emitCurIGsize += sz; } +#endif // !LEGACY_BACKEND + /***************************************************************************** * * Add an instruction with a register + static member operands. @@ -5251,7 +5243,7 @@ void emitter::emitIns_AX_R(instruction ins, emitAttr attr, regNumber ireg, regNu emitAdjustStackDepthPushPop(ins); } -#if FEATURE_HW_INTRINSICS +#ifdef FEATURE_HW_INTRINSICS void emitter::emitIns_SIMD_R_R_A(instruction ins, emitAttr attr, regNumber reg, regNumber reg1, GenTreeIndir* indir) { if (UseVEXEncoding()) @@ -7738,7 +7730,7 @@ void emitter::emitDispIns( // INS_bt operands are reversed. Display them in the normal order. printf("%s, %s", emitRegName(id->idReg2(), attr), emitRegName(id->idReg1(), attr)); } -#if FEATURE_HW_INTRINSICS +#ifdef FEATURE_HW_INTRINSICS else if (ins == INS_crc32 && attr != EA_8BYTE) { printf("%s, %s", emitRegName(id->idReg1(), EA_4BYTE), emitRegName(id->idReg2(), attr)); @@ -10108,7 +10100,7 @@ BYTE* emitter::emitOutputRR(BYTE* dst, instrDesc* id) #endif // _TARGET_AMD64_ } -#if FEATURE_HW_INTRINSICS +#ifdef FEATURE_HW_INTRINSICS else if ((ins == INS_crc32) || (ins == INS_lzcnt) || (ins == INS_popcnt)) { code = insEncodeRMreg(ins, code); diff --git a/src/jit/emitxarch.h b/src/jit/emitxarch.h index f2e426d07a..74fdc84a0c 100644 --- a/src/jit/emitxarch.h +++ b/src/jit/emitxarch.h @@ -184,6 +184,14 @@ bool IsThreeOperandAVXInstruction(instruction ins) return (IsDstDstSrcAVXInstruction(ins) || IsDstSrcSrcAVXInstruction(ins)); } bool Is4ByteAVXInstruction(instruction ins); +bool isAvxBlendv(instruction ins) +{ + return ins == INS_vblendvps || ins == INS_vblendvpd || ins == INS_vpblendvb; +} +bool isSse41Blendv(instruction ins) +{ + return ins == INS_blendvps || ins == INS_blendvpd || ins == INS_pblendvb; +} #else // LEGACY_BACKEND bool UseVEXEncoding() { @@ -226,6 +234,14 @@ bool Is4ByteAVXInstruction(instruction ins) { return false; } +bool isAvxBlendv(instruction ins) +{ + return false; +} +bool isSse41Blendv(instruction ins) +{ + return false; +} bool TakesVexPrefix(instruction ins) { return false; @@ -398,7 +414,9 @@ void emitIns_R_R_R_I(instruction ins, emitAttr attr, regNumber reg1, regNumber r void emitIns_R_R_S_I(instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, int varx, int offs, int ival); +#ifndef LEGACY_BACKEND void emitIns_R_R_R_R(instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, regNumber reg3, regNumber reg4); +#endif // !LEGACY_BACKEND void emitIns_S(instruction ins, emitAttr attr, int varx, int offs); @@ -454,7 +472,7 @@ void emitIns_R_AX(instruction ins, emitAttr attr, regNumber ireg, regNumber reg, void emitIns_AX_R(instruction ins, emitAttr attr, regNumber ireg, regNumber reg, unsigned mul, int disp); -#if FEATURE_HW_INTRINSICS +#ifdef FEATURE_HW_INTRINSICS void emitIns_SIMD_R_R_AR(instruction ins, emitAttr attr, regNumber reg, regNumber reg1, regNumber base); void emitIns_SIMD_R_R_A_I(instruction ins, emitAttr attr, regNumber reg, regNumber reg1, GenTreeIndir* indir, int ival); void emitIns_SIMD_R_R_C_I( @@ -468,7 +486,7 @@ void emitIns_SIMD_R_R_S(instruction ins, emitAttr attr, regNumber reg, regNumber void emitIns_SIMD_R_R_R(instruction ins, emitAttr attr, regNumber reg, regNumber reg1, regNumber reg2); void emitIns_SIMD_R_R_R_R( instruction ins, emitAttr attr, regNumber reg, regNumber reg1, regNumber reg2, regNumber reg3); -#endif +#endif // FEATURE_HW_INTRINSICS #if FEATURE_STACK_FP_X87 void emitIns_F_F0(instruction ins, unsigned fpreg); diff --git a/src/jit/gentree.cpp b/src/jit/gentree.cpp index 5d1fdc2f60..08f84515a7 100644 --- a/src/jit/gentree.cpp +++ b/src/jit/gentree.cpp @@ -1425,7 +1425,7 @@ AGAIN: break; #endif // FEATURE_SIMD -#if FEATURE_HW_INTRINSICS +#ifdef FEATURE_HW_INTRINSICS case GT_HWIntrinsic: if ((op1->AsHWIntrinsic()->gtHWIntrinsicId != op2->AsHWIntrinsic()->gtHWIntrinsicId) || (op1->AsHWIntrinsic()->gtSIMDBaseType != op2->AsHWIntrinsic()->gtSIMDBaseType) || @@ -2110,7 +2110,7 @@ AGAIN: break; #endif // FEATURE_SIMD -#if FEATURE_HW_INTRINSICS +#ifdef FEATURE_HW_INTRINSICS case GT_HWIntrinsic: hash += tree->gtHWIntrinsic.gtHWIntrinsicId; hash += tree->gtHWIntrinsic.gtSIMDBaseType; @@ -7929,7 +7929,7 @@ GenTreePtr Compiler::gtCloneExpr( break; #endif -#if FEATURE_HW_INTRINSICS +#ifdef FEATURE_HW_INTRINSICS case GT_HWIntrinsic: { GenTreeHWIntrinsic* hwintrinsicOp = tree->AsHWIntrinsic(); @@ -9235,7 +9235,7 @@ GenTreeUseEdgeIterator::GenTreeUseEdgeIterator(GenTree* node) return; #endif // FEATURE_SIMD -#if FEATURE_HW_INTRINSICS +#ifdef FEATURE_HW_INTRINSICS case GT_HWIntrinsic: if (m_node->AsHWIntrinsic()->gtOp1 == nullptr) { @@ -11268,7 +11268,7 @@ extern const char* const simdIntrinsicNames[] = { }; #endif // FEATURE_SIMD -#if FEATURE_HW_INTRINSICS +#ifdef FEATURE_HW_INTRINSICS extern const char* getHWIntrinsicName(NamedIntrinsic intrinsic); #endif // FEATURE_HW_INTRINSICS @@ -11606,7 +11606,7 @@ void Compiler::gtDispTree(GenTreePtr tree, } #endif // FEATURE_SIMD -#if FEATURE_HW_INTRINSICS +#ifdef FEATURE_HW_INTRINSICS if (tree->gtOper == GT_HWIntrinsic) { printf(" %s %s", @@ -17102,7 +17102,7 @@ CORINFO_CLASS_HANDLE Compiler::gtGetStructHandleIfPresent(GenTree* tree) structHnd = gtGetStructHandleForSIMD(tree->gtType, tree->AsSIMD()->gtSIMDBaseType); break; #endif // FEATURE_SIMD -#if FEATURE_HW_INTRINSICS +#ifdef FEATURE_HW_INTRINSICS case GT_HWIntrinsic: structHnd = gtGetStructHandleForHWSIMD(tree->gtType, tree->AsHWIntrinsic()->gtSIMDBaseType); break; @@ -17904,7 +17904,7 @@ bool GenTree::isCommutativeSIMDIntrinsic() } #endif // FEATURE_SIMD -#if FEATURE_HW_INTRINSICS +#ifdef FEATURE_HW_INTRINSICS GenTreeHWIntrinsic* Compiler::gtNewSimdHWIntrinsicNode(var_types type, NamedIntrinsic hwIntrinsicID, var_types baseType, diff --git a/src/jit/gentree.h b/src/jit/gentree.h index d66c835fb6..fb4d0e8272 100644 --- a/src/jit/gentree.h +++ b/src/jit/gentree.h @@ -1593,7 +1593,7 @@ public: return OperIsSIMD(gtOper); } -#if FEATURE_HW_INTRINSICS +#ifdef FEATURE_HW_INTRINSICS inline bool OperIsSimdHWIntrinsic() const; #else inline bool OperIsSimdHWIntrinsic() const @@ -1663,7 +1663,7 @@ public: case GT_LEA: case GT_RETFILT: case GT_NOP: -#if FEATURE_HW_INTRINSICS +#ifdef FEATURE_HW_INTRINSICS case GT_HWIntrinsic: #endif // FEATURE_HW_INTRINSICS return true; @@ -1691,7 +1691,7 @@ public: case GT_SIMD: #endif // !FEATURE_SIMD -#if FEATURE_HW_INTRINSICS +#ifdef FEATURE_HW_INTRINSICS case GT_HWIntrinsic: #endif // FEATURE_HW_INTRINSICS @@ -4223,7 +4223,7 @@ struct GenTreeSIMD : public GenTreeJitIntrinsic }; #endif // FEATURE_SIMD -#if FEATURE_HW_INTRINSICS +#ifdef FEATURE_HW_INTRINSICS struct GenTreeHWIntrinsic : public GenTreeJitIntrinsic { NamedIntrinsic gtHWIntrinsicId; diff --git a/src/jit/gtlist.h b/src/jit/gtlist.h index 6c6b76e4bf..fde7aa370e 100644 --- a/src/jit/gtlist.h +++ b/src/jit/gtlist.h @@ -224,7 +224,7 @@ GTNODE(RSH_LO , GenTreeOp ,0,GTK_BINOP) GTNODE(SIMD , GenTreeSIMD ,0,GTK_BINOP|GTK_EXOP) // SIMD functions/operators/intrinsics #endif // FEATURE_SIMD -#if FEATURE_HW_INTRINSICS +#ifdef FEATURE_HW_INTRINSICS GTNODE(HWIntrinsic , GenTreeHWIntrinsic ,0,GTK_BINOP|GTK_EXOP) // hardware intrinsics #endif // FEATURE_HW_INTRINSICS diff --git a/src/jit/gtstructs.h b/src/jit/gtstructs.h index 99e68c7adb..f3ff0217f2 100644 --- a/src/jit/gtstructs.h +++ b/src/jit/gtstructs.h @@ -117,7 +117,7 @@ GTSTRUCT_1(PhysReg , GT_PHYSREG) #ifdef FEATURE_SIMD GTSTRUCT_1(SIMD , GT_SIMD) #endif // FEATURE_SIMD -#if FEATURE_HW_INTRINSICS +#ifdef FEATURE_HW_INTRINSICS GTSTRUCT_1(HWIntrinsic , GT_HWIntrinsic) #endif // FEATURE_HW_INTRINSICS GTSTRUCT_1(AllocObj , GT_ALLOCOBJ) diff --git a/src/jit/importer.cpp b/src/jit/importer.cpp index b81406e051..0321bc2213 100644 --- a/src/jit/importer.cpp +++ b/src/jit/importer.cpp @@ -1613,7 +1613,7 @@ GenTreePtr Compiler::impNormStructVal(GenTreePtr structVal, assert(varTypeIsSIMD(structVal) && (structVal->gtType == structType)); break; #endif // FEATURE_SIMD -#if FEATURE_HW_INTRINSICS +#ifdef FEATURE_HW_INTRINSICS case GT_HWIntrinsic: assert(varTypeIsSIMD(structVal) && (structVal->gtType == structType)); break; @@ -1652,7 +1652,7 @@ GenTreePtr Compiler::impNormStructVal(GenTreePtr structVal, } else #endif -#if FEATURE_HW_INTRINSICS +#ifdef FEATURE_HW_INTRINSICS if (blockNode->OperGet() == GT_HWIntrinsic && blockNode->AsHWIntrinsic()->isSIMD()) { parent->gtOp.gtOp2 = impNormStructVal(blockNode, structHnd, curLevel, forceNormalization); @@ -3395,7 +3395,7 @@ GenTree* Compiler::impIntrinsic(GenTree* newobjThis, { ni = lookupNamedIntrinsic(method); -#if FEATURE_HW_INTRINSICS +#ifdef FEATURE_HW_INTRINSICS #ifdef _TARGET_XARCH_ if (ni > NI_HW_INTRINSIC_START && ni < NI_HW_INTRINSIC_END) { @@ -4118,13 +4118,13 @@ NamedIntrinsic Compiler::lookupNamedIntrinsic(CORINFO_METHOD_HANDLE method) } } -#if FEATURE_HW_INTRINSICS && defined(_TARGET_XARCH_) +#if defined(FEATURE_HW_INTRINSICS) && defined(_TARGET_XARCH_) if ((namespaceName != nullptr) && strcmp(namespaceName, "System.Runtime.Intrinsics.X86") == 0) { InstructionSet isa = lookupHWIntrinsicISA(className); result = lookupHWIntrinsic(methodName, isa); } -#endif // FEATURE_HW_INTRINSICS +#endif // defined(FEATURE_HW_INTRINSICS) && defined(_TARGET_XARCH_) return result; } diff --git a/src/jit/lsra.h b/src/jit/lsra.h index 2249ebd593..1fbaaa2d3b 100644 --- a/src/jit/lsra.h +++ b/src/jit/lsra.h @@ -1587,7 +1587,7 @@ private: void TreeNodeInfoInitSIMD(GenTreeSIMD* tree, TreeNodeInfo* info); #endif // FEATURE_SIMD -#if FEATURE_HW_INTRINSICS +#ifdef FEATURE_HW_INTRINSICS void TreeNodeInfoInitHWIntrinsic(GenTreeHWIntrinsic* intrinsicTree, TreeNodeInfo* info); #endif // FEATURE_HW_INTRINSICS diff --git a/src/jit/lsraxarch.cpp b/src/jit/lsraxarch.cpp index c0a9bc8c54..fc28f01c78 100644 --- a/src/jit/lsraxarch.cpp +++ b/src/jit/lsraxarch.cpp @@ -362,7 +362,7 @@ void LinearScan::TreeNodeInfoInit(GenTree* tree, TreeNodeInfo* info) break; #endif // FEATURE_SIMD -#if FEATURE_HW_INTRINSICS +#ifdef FEATURE_HW_INTRINSICS case GT_HWIntrinsic: TreeNodeInfoInitHWIntrinsic(tree->AsHWIntrinsic(), info); break; @@ -2481,7 +2481,7 @@ void LinearScan::TreeNodeInfoInitSIMD(GenTreeSIMD* simdTree, TreeNodeInfo* info) } #endif // FEATURE_SIMD -#if FEATURE_HW_INTRINSICS +#ifdef FEATURE_HW_INTRINSICS //------------------------------------------------------------------------ // TreeNodeInfoInitHWIntrinsic: Set the NodeInfo for a GT_HWIntrinsic tree. // diff --git a/src/jit/simd.cpp b/src/jit/simd.cpp index b91c8e759b..e6936c54a3 100644 --- a/src/jit/simd.cpp +++ b/src/jit/simd.cpp @@ -348,7 +348,7 @@ var_types Compiler::getBaseTypeAndSizeOfSIMDType(CORINFO_CLASS_HANDLE typeHnd, u setUsesSIMDTypes(true); } } -#if FEATURE_HW_INTRINSICS +#ifdef FEATURE_HW_INTRINSICS else if (isIntrinsicType(typeHnd)) { const size_t Vector64SizeBytes = 64 / 8; diff --git a/src/jit/valuenum.cpp b/src/jit/valuenum.cpp index 7fed0e0392..9ca852e5a2 100644 --- a/src/jit/valuenum.cpp +++ b/src/jit/valuenum.cpp @@ -5614,7 +5614,7 @@ void Compiler::fgValueNumberTree(GenTreePtr tree, bool evalAsgLhsInd) } #endif -#if FEATURE_HW_INTRINSICS +#ifdef FEATURE_HW_INTRINSICS if (oper == GT_HWIntrinsic) { // TODO-CQ: For now hardware intrinsics are not handled by value numbering to be amenable for CSE'ing. |