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| author | Steve MacLean <sdmaclea.qdt@qualcommdatacenter.com> | 2017-11-02 12:26:46 -0400 |
|---|---|---|
| committer | Steve MacLean <sdmaclea.qdt@qualcommdatacenter.com> | 2017-11-02 12:55:48 -0400 |
| commit | d046e74002af772b41b75f3752b25d9300e47a62 (patch) | |
| tree | 79f9bbb4be5988d82b5744891adc0dcbacedbe2c /src | |
| parent | 762387ad7bb7a7c351a7f0a2cc8cf71956aa14fc (diff) | |
| download | coreclr-d046e74002af772b41b75f3752b25d9300e47a62.tar.gz coreclr-d046e74002af772b41b75f3752b25d9300e47a62.tar.bz2 coreclr-d046e74002af772b41b75f3752b25d9300e47a62.zip | |
[Arm64] genSIMDIntrinsicRelOp
Handle SIMD12 special case
Diffstat (limited to 'src')
| -rw-r--r-- | src/jit/codegenarm64.cpp | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/jit/codegenarm64.cpp b/src/jit/codegenarm64.cpp index d559c92c81..fe71390d7e 100644 --- a/src/jit/codegenarm64.cpp +++ b/src/jit/codegenarm64.cpp @@ -4365,6 +4365,14 @@ void CodeGen::genSIMDIntrinsicRelOp(GenTreeSIMD* simdNode) getEmitter()->emitIns_R_R_R(ins, attr, tmpFloatReg, op1Reg, op2Reg, opt); + if ((simdNode->gtFlags & GTF_SIMD12_OP) != 0) + { + // For 12Byte vectors we must set upper bits to get correct comparison + // We do not assume upper bits are zero. + instGen_Set_Reg_To_Imm(EA_4BYTE, targetReg, -1); + getEmitter()->emitIns_R_R_I(INS_ins, EA_4BYTE, tmpFloatReg, targetReg, 3); + } + getEmitter()->emitIns_R_R(INS_uminv, attr, tmpFloatReg, tmpFloatReg, (simdNode->gtSIMDSize > 8) ? INS_OPTS_16B : INS_OPTS_8B); |