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| author | Bruce Forstall <brucefo@microsoft.com> | 2017-11-01 16:37:09 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2017-11-01 16:37:09 -0700 |
| commit | aa24cd3e019bda4f2a98295ac0fe6888a554d372 (patch) | |
| tree | e7b66359f435fe1aeb18d32ddb64b1aa0accf866 /src | |
| parent | 6b65367881160f445d421bf05269eb57e5c0d4c7 (diff) | |
| parent | 6ec2b8830eadeff43fe922644d29b3e4100331e0 (diff) | |
| download | coreclr-aa24cd3e019bda4f2a98295ac0fe6888a554d372.tar.gz coreclr-aa24cd3e019bda4f2a98295ac0fe6888a554d372.tar.bz2 coreclr-aa24cd3e019bda4f2a98295ac0fe6888a554d372.zip | |
Merge pull request #14808 from sdmaclea/PR-ARM64-genSIMDIntrinsicDotProduct
[Arm64] Fix genSIMDIntrinsicDotProduct
Diffstat (limited to 'src')
| -rw-r--r-- | src/jit/codegenarm64.cpp | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/src/jit/codegenarm64.cpp b/src/jit/codegenarm64.cpp index 89fe0c92e3..d559c92c81 100644 --- a/src/jit/codegenarm64.cpp +++ b/src/jit/codegenarm64.cpp @@ -4423,6 +4423,13 @@ void CodeGen::genSIMDIntrinsicDotProduct(GenTreeSIMD* simdNode) // Vector multiply getEmitter()->emitIns_R_R_R(ins, attr, tmpReg, op1Reg, op2Reg, opt); + if ((simdNode->gtFlags & GTF_SIMD12_OP) != 0) + { + // For 12Byte vectors we must zero upper bits to get correct dot product + // We do not assume upper bits are zero. + getEmitter()->emitIns_R_R_I(INS_ins, EA_4BYTE, tmpReg, REG_ZR, 3); + } + // Vector add horizontal if (varTypeIsFloating(baseType)) { @@ -4432,11 +4439,11 @@ void CodeGen::genSIMDIntrinsicDotProduct(GenTreeSIMD* simdNode) { getEmitter()->emitIns_R_R_R(INS_faddp, attr, tmpReg, tmpReg, tmpReg, INS_OPTS_4S); } - getEmitter()->emitIns_R_R(INS_faddp, EA_8BYTE, targetReg, tmpReg, INS_OPTS_2S); + getEmitter()->emitIns_R_R(INS_faddp, EA_4BYTE, targetReg, tmpReg); } else { - getEmitter()->emitIns_R_R(INS_faddp, EA_16BYTE, targetReg, tmpReg, INS_OPTS_2D); + getEmitter()->emitIns_R_R(INS_faddp, EA_8BYTE, targetReg, tmpReg); } } else |