Deal with cross-bitness compilation warnings Pt.2 (#19781)

* Disable ASMCONSTANTS_C_ASSERT in cross-bitness scenario in src/vm/ceeload.cpp

* Adjust MAXFIELDMARSHALERSIZE for cross-bitness scenario in src/vm/arm/cgencpu.h

* Make ALLOC_ALIGN_CONSTANT host specific in src/inc/stdmacros.h

* Make PRECODE_ALIGNMENT host specific in src/vm/arm/cgencpu.h

* Disable unreachable code in src/vm/arm/stubs.cpp

* Adjust CorDBIPC_BUFFER_SIZE for cross-bitness scenario in src/debug/inc/dbgipcevents.h

* Disable warning C4359 in src/vm/arm/cgencpu.h

* Deal with warning C4267: 'initializing': conversion from 'size_t' to 'int' in src/vm/stublink.cpp

* Deal with warning C4267: 'initializing': conversion from 'size_t' to 'int' in src/vm/callingconvention.h

* Disable unreachable REGDISPLAY constructor in src/inc/regdisp.h

2 files changed, 18 insertions, 4 deletions

diff --git a/src/vm/arm/cgencpu.h b/src/vm/arm/cgencpu.h
index 745626bd40..62891170c4 100644
--- a/src/vm/arm/cgencpu.h
+++ b/src/vm/arm/cgencpu.h
@@ -102,7 +102,11 @@ EXTERN_C void setFPReturn(int fpSize, INT64 retVal);
 // as large as the largest FieldMarshaler subclass. This requirement
 // is guarded by an assert.
 //=======================================================================
+#ifdef _WIN64
+#define MAXFIELDMARSHALERSIZE               40
+#else
 #define MAXFIELDMARSHALERSIZE               24
+#endif
 
 //**********************************************************************
 // Parameter size
@@ -985,6 +989,11 @@ inline BOOL IsUnmanagedValueTypeReturnedByRef(UINT sizeofvaluetype)
     return (sizeofvaluetype > 4);
 }
 
+#ifdef _MSC_VER
+#pragma warning(push)
+#pragma warning(disable:4359) // Prevent "warning C4359: 'UMEntryThunkCode': Alignment specifier is less than actual alignment (8), and will be ignored." in crossbitness scenario
+#endif // _MSC_VER
+
 struct DECLSPEC_ALIGN(4) UMEntryThunkCode
 {
     WORD        m_code[4];
@@ -1010,6 +1019,10 @@ struct DECLSPEC_ALIGN(4) UMEntryThunkCode
     }
 };
 
+#ifdef _MSC_VER
+#pragma warning(pop)
+#endif // _MSC_VER
+
 struct HijackArgs
 {
     union
@@ -1082,7 +1095,7 @@ inline BOOL ClrFlushInstructionCache(LPCVOID pCodeAddr, size_t sizeOfCode)
 
 EXTERN_C VOID STDCALL PrecodeFixupThunk();
 
-#define PRECODE_ALIGNMENT           CODE_SIZE_ALIGN
+#define PRECODE_ALIGNMENT           sizeof(void*)
 #define SIZEOF_PRECODE_BASE         CODE_SIZE_ALIGN
 #define OFFSETOF_PRECODE_TYPE       0
 
diff --git a/src/vm/arm/stubs.cpp b/src/vm/arm/stubs.cpp
index bd3ad515c9..d2ee3b7c3e 100644
--- a/src/vm/arm/stubs.cpp
+++ b/src/vm/arm/stubs.cpp
@@ -1678,6 +1678,8 @@ VOID StubLinkerCPU::EmitShuffleThunk(ShuffleEntry *pShuffleEntryArray)
     ThumbEmitEpilog();
 }
 
+#ifndef CROSSGEN_COMPILE
+
 void StubLinkerCPU::ThumbEmitCallManagedMethod(MethodDesc *pMD, bool fTailcall)
 {
     bool isRelative = MethodTable::VTableIndir2_t::isRelative
@@ -1747,7 +1749,6 @@ void StubLinkerCPU::ThumbEmitCallManagedMethod(MethodDesc *pMD, bool fTailcall)
     }
 }
 
-#ifndef CROSSGEN_COMPILE
 // Common code used to generate either an instantiating method stub or an unboxing stub (in the case where the
 // unboxing stub also needs to provide a generic instantiation parameter). The stub needs to add the
 // instantiation parameter provided in pHiddenArg and re-arrange the rest of the incoming arguments as a
@@ -2368,7 +2369,6 @@ void TailCallFrame::InitFromContext(T_CONTEXT * pContext)
 }
 
 #endif // !DACCESS_COMPILE
-#endif // !CROSSGEN_COMPILE
 
 void FaultingExceptionFrame::UpdateRegDisplay(const PREGDISPLAY pRD) 
 { 
@@ -2527,7 +2527,8 @@ void HijackFrame::UpdateRegDisplay(const PREGDISPLAY pRD)
 
      SyncRegDisplayToCurrentContext(pRD);
 }
-#endif
+#endif // FEATURE_HIJACK
+#endif // !CROSSGEN_COMPILE
 
 class UMEntryThunk * UMEntryThunk::Decode(void *pCallback)
 {