diff options
| author | Steve MacLean <Steve.MacLean@microsoft.com> | 2019-07-16 10:06:52 -0400 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-07-16 10:06:52 -0400 |
| commit | f5b1b889a0480eecf7068db4a17e8dd35a7ed878 (patch) | |
| tree | c5545bd368ee781b529681715371a0286d758899 /src/vm/arm64 | |
| parent | 2d52fd7ae5ebb4c1ba97a27a19e6d517c26b117a (diff) | |
| download | coreclr-f5b1b889a0480eecf7068db4a17e8dd35a7ed878.tar.gz coreclr-f5b1b889a0480eecf7068db4a17e8dd35a7ed878.tar.bz2 coreclr-f5b1b889a0480eecf7068db4a17e8dd35a7ed878.zip | |
Add missing Arm64 specific diagnostic code (#25695)
* Arm64 ICorDebugRegisterSet float support
* Arm64 ICorDebugRegisterSet2 implementation
* Add arm64 VLT_REG_FP case
* Arm64 add funceval GetRegister SetRegister support
Diffstat (limited to 'src/vm/arm64')
| -rw-r--r-- | src/vm/arm64/cgencpu.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/vm/arm64/cgencpu.h b/src/vm/arm64/cgencpu.h index 997ad7d60f..9a5fc84420 100644 --- a/src/vm/arm64/cgencpu.h +++ b/src/vm/arm64/cgencpu.h @@ -71,6 +71,21 @@ extern PCODE GetPreStubEntryPoint(); //======================================================================= #define MAXFIELDMARSHALERSIZE 40 +inline +ARG_SLOT FPSpillToR8(void* pSpillSlot) +{ + LIMITED_METHOD_CONTRACT; + return *(SIZE_T*)pSpillSlot; +} + +inline +void R8ToFPSpill(void* pSpillSlot, SIZE_T srcDoubleAsSIZE_T) +{ + LIMITED_METHOD_CONTRACT; + *(SIZE_T*)pSpillSlot = srcDoubleAsSIZE_T; + *((SIZE_T*)pSpillSlot + 1) = 0; +} + //********************************************************************** // Parameter size //********************************************************************** |