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| author | Steve MacLean, Qualcomm Datacenter Technologies, Inc <sdmaclea@qti.qualcomm.com> | 2017-05-26 00:08:34 +0000 |
|---|---|---|
| committer | Russ Keldorph <russ.keldorph@microsoft.com> | 2017-06-08 08:54:37 -0700 |
| commit | 56d40339e615ea035883f60fc77a91b6be5c4445 (patch) | |
| tree | 234238521d3e012ef2ed5c26327e246f68b302d3 /src/vm/arm64/asmhelpers.asm | |
| parent | d9526fde97edf79822380f437e0058c5f8988d2f (diff) | |
| download | coreclr-56d40339e615ea035883f60fc77a91b6be5c4445.tar.gz coreclr-56d40339e615ea035883f60fc77a91b6be5c4445.tar.bz2 coreclr-56d40339e615ea035883f60fc77a91b6be5c4445.zip | |
[Arm64] Use ish domain JIT_WriteBarrier
Diffstat (limited to 'src/vm/arm64/asmhelpers.asm')
| -rw-r--r-- | src/vm/arm64/asmhelpers.asm | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/vm/arm64/asmhelpers.asm b/src/vm/arm64/asmhelpers.asm index 24b26eb1c9..f303f82ff6 100644 --- a/src/vm/arm64/asmhelpers.asm +++ b/src/vm/arm64/asmhelpers.asm @@ -326,7 +326,7 @@ NotInHeap ; x15 : trashed ; WRITE_BARRIER_ENTRY JIT_WriteBarrier - dmb ST + dmb ish str x15, [x14] #ifdef WRITE_BARRIER_CHECK @@ -355,7 +355,7 @@ NotInHeap ; Ensure that the write to the shadow heap occurs before the read from the GC heap so that race ; conditions are caught by INVALIDGCVALUE. - dmb sy + dmb ish ; if ([x14] == x15) goto end ldr x13, [x14] |