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| author | Jacek Blaszczynski <biosciencenow@outlook.com> | 2018-03-22 22:17:35 +0100 |
|---|---|---|
| committer | Eric Erhardt <eric.erhardt@microsoft.com> | 2018-03-26 20:53:15 -0500 |
| commit | 37bd5d89ce760b412026296bd5a77495a1f80734 (patch) | |
| tree | a2967b384344a20476b9363e3dc31c7a660f1db8 /src/jit | |
| parent | 13dfb52d269fb94fd7e0dd13b42cb3ab20ed47e9 (diff) | |
| download | coreclr-37bd5d89ce760b412026296bd5a77495a1f80734.tar.gz coreclr-37bd5d89ce760b412026296bd5a77495a1f80734.tar.bz2 coreclr-37bd5d89ce760b412026296bd5a77495a1f80734.zip | |
Enable partially implemented Intel HW intrinsics ISAs - CoreCLR part of changes
Diffstat (limited to 'src/jit')
| -rw-r--r-- | src/jit/hwintrinsicxarch.cpp | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/src/jit/hwintrinsicxarch.cpp b/src/jit/hwintrinsicxarch.cpp index 1c80714918..9da218fc48 100644 --- a/src/jit/hwintrinsicxarch.cpp +++ b/src/jit/hwintrinsicxarch.cpp @@ -540,15 +540,14 @@ GenTree* Compiler::addRangeCheckIfNeeded(NamedIntrinsic intrinsic, GenTree* last // Arguments: // isa - Instruction set // Return Value: -// true - all the hardware intrinsics of "isa" are implemented in RyuJIT. +// true - all the hardware intrinsics of "isa" exposed in CoreFX +// System.Runtime.Intrinsics.Experimental assembly are implemented in RyuJIT. // bool Compiler::isFullyImplmentedISAClass(InstructionSet isa) { switch (isa) { - case InstructionSet_SSE42: - case InstructionSet_AVX: - case InstructionSet_AVX2: + // These ISAs have no implementation case InstructionSet_AES: case InstructionSet_BMI1: case InstructionSet_BMI2: @@ -556,6 +555,13 @@ bool Compiler::isFullyImplmentedISAClass(InstructionSet isa) case InstructionSet_PCLMULQDQ: return false; + // These ISAs are partially implemented + case InstructionSet_AVX: + case InstructionSet_AVX2: + case InstructionSet_SSE42: + return true; + + // These ISAs are fully implemented case InstructionSet_SSE: case InstructionSet_SSE2: case InstructionSet_SSE3: |