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| author | Brian Sullivan <briansul@microsoft.com> | 2015-12-11 16:16:44 -0800 |
|---|---|---|
| committer | Brian Sullivan <briansul@microsoft.com> | 2015-12-11 16:16:44 -0800 |
| commit | 121d095ed0b0076fb1c7ff59e6446fd19d506b32 (patch) | |
| tree | 4a690f67e0117dd346a9de1937f018918a970ae9 /src/jit/typelist.h | |
| parent | f05270a77a9782c5960d1bdff82b8521b1e3fa5d (diff) | |
| download | coreclr-121d095ed0b0076fb1c7ff59e6446fd19d506b32.tar.gz coreclr-121d095ed0b0076fb1c7ff59e6446fd19d506b32.tar.bz2 coreclr-121d095ed0b0076fb1c7ff59e6446fd19d506b32.zip | |
Port of all JIT changes for .NET Framework 4.6.1 changes
http://blogs.msdn.com/b/dotnet/archive/2015/11/30/net-framework-4-6-1-is-now-available.aspx
.NET Framework list of changes in 4.6.1
https://github.com/Microsoft/dotnet/blob/master/releases/net461/dotnet461-changes.md
Additional changes including
- Working ARM64 JIT compiler
- Additional JIT Optimizations
o Tail call recursion optimization
o Array length tracking optimization
o CSE for widening casts
o Smaller encoding for RIP relative and absolute addresses in addressing modes
o Tracked Local Variable increased to 512
o Improved handling of Intrinsics System.GetType()
o Improved handling of Math intrinsics
- Work for the X86 Ryu-JIT compiler
[tfs-changeset: 1557101]
Diffstat (limited to 'src/jit/typelist.h')
| -rw-r--r-- | src/jit/typelist.h | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/src/jit/typelist.h b/src/jit/typelist.h index ec33e7b1f4..86ad095ad2 100644 --- a/src/jit/typelist.h +++ b/src/jit/typelist.h @@ -54,7 +54,7 @@ DEF_TP(DOUBLE ,"double" , TYP_DOUBLE, TI_DOUBLE,8, 8, 8, 2, 8, VTF_FLT, DEF_TP(REF ,"ref" , TYP_REF, TI_REF, PS,GCS,GCS, PST,PS, VTF_ANY|VTF_GCR|VTF_I,TYPE_REF_PTR) DEF_TP(BYREF ,"byref" , TYP_BYREF, TI_ERROR,PS,BRS,BRS, PST,PS, VTF_ANY|VTF_BYR|VTF_I,TYPE_REF_BYR) DEF_TP(ARRAY ,"array" , TYP_REF, TI_REF, PS,GCS,GCS, PST,PS, VTF_ANY|VTF_GCR|VTF_I,TYPE_REF_PTR) -DEF_TP(STRUCT ,"struct" , TYP_STRUCT, TI_STRUCT,0, 0, 0, 1, 4, VTF_ANY, TYPE_REF_STC) +DEF_TP(STRUCT ,"struct" , TYP_STRUCT, TI_STRUCT,0, 0, 0, 1, 4, VTF_S, TYPE_REF_STC) DEF_TP(BLK ,"blk" , TYP_BLK, TI_ERROR, 0, 0, 0, 1, 4, VTF_ANY, 0 ) // blob of memory DEF_TP(LCLBLK ,"lclBlk" , TYP_LCLBLK, TI_ERROR, 0, 0, 0, 1, 4, VTF_ANY, 0 ) // preallocated memory for locspace @@ -64,9 +64,10 @@ DEF_TP(FNC ,"function", TYP_FNC, TI_ERROR, 0, PS, PS, 0, 0, VTF_ANY|VT #ifdef FEATURE_SIMD // Amd64: The size and alignment of SIMD vector varies at JIT time based on whether target arch supports AVX or SSE2. -DEF_TP(SIMD12 ,"simd12" , TYP_SIMD16, TI_STRUCT,12,12, 16, 4,16, VTF_ANY, TYPE_REF_STC) -DEF_TP(SIMD16 ,"simd16" , TYP_SIMD16, TI_STRUCT,16,16, 16, 4,16, VTF_ANY, TYPE_REF_STC) -DEF_TP(SIMD32 ,"simd32" , TYP_SIMD32, TI_STRUCT,32,32, 32, 8,16, VTF_ANY, TYPE_REF_STC) +DEF_TP(SIMD8 ,"simd8" , TYP_SIMD8, TI_STRUCT, 8, 8, 8, 2, 8, VTF_S, TYPE_REF_STC) +DEF_TP(SIMD12 ,"simd12" , TYP_SIMD12, TI_STRUCT,12,16, 16, 4,16, VTF_S, TYPE_REF_STC) +DEF_TP(SIMD16 ,"simd16" , TYP_SIMD16, TI_STRUCT,16,16, 16, 4,16, VTF_S, TYPE_REF_STC) +DEF_TP(SIMD32 ,"simd32" , TYP_SIMD32, TI_STRUCT,32,32, 32, 8,16, VTF_S, TYPE_REF_STC) #endif // FEATURE_SIMD DEF_TP(UNKNOWN ,"unknown" ,TYP_UNKNOWN, TI_ERROR, 0, 0, 0, 0, 0, VTF_ANY, 0 ) |