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| author | Carol Eidt <carol.eidt@microsoft.com> | 2017-10-24 14:18:09 -0700 |
|---|---|---|
| committer | Carol Eidt <carol.eidt@microsoft.com> | 2017-10-25 09:17:16 -0700 |
| commit | bc927933932d6b231d50432398069691c713eb44 (patch) | |
| tree | 0eeebaf6c6428b7156451f9158c6195a6479cefd /src/jit/target.h | |
| parent | 33a5f24d349c327cc508d0136845fd3bf8cac631 (diff) | |
| download | coreclr-bc927933932d6b231d50432398069691c713eb44.tar.gz coreclr-bc927933932d6b231d50432398069691c713eb44.tar.bz2 coreclr-bc927933932d6b231d50432398069691c713eb44.zip | |
Avoid allocating IP0 and IP1
Revert to prior behavior.
Diffstat (limited to 'src/jit/target.h')
| -rw-r--r-- | src/jit/target.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/jit/target.h b/src/jit/target.h index 37919e2422..ad36689346 100644 --- a/src/jit/target.h +++ b/src/jit/target.h @@ -1604,7 +1604,6 @@ typedef unsigned short regPairNoSmall; // arm: need 12 bits #define REG_VAR_ORDER REG_R9,REG_R10,REG_R11,REG_R12,REG_R13,REG_R14,REG_R15,\ REG_R8,REG_R7,REG_R6,REG_R5,REG_R4,REG_R3,REG_R2,REG_R1,REG_R0,\ REG_R19,REG_R20,REG_R21,REG_R22,REG_R23,REG_R24,REG_R25,REG_R26,REG_R27,REG_R28,\ - REG_IP0,REG_IP1,\ #define REG_VAR_ORDER_FLT REG_V16, REG_V17, REG_V18, REG_V19, \ REG_V20, REG_V21, REG_V22, REG_V23, \ |