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| author | Carol Eidt <carol.eidt@microsoft.com> | 2017-10-20 11:20:17 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2017-10-20 11:20:17 -0700 |
| commit | ae991c3a6042256c25d6c82e2714cd41eb14798a (patch) | |
| tree | 1211bd8aac0d1fa319b01ff25b362b2e708d0ad2 /src/jit/target.h | |
| parent | 51f904d67b6bd693cc40095f802ab9afd80146ea (diff) | |
| parent | a4d2ebd2c865e217c2ba558b136609297f76988f (diff) | |
| download | coreclr-ae991c3a6042256c25d6c82e2714cd41eb14798a.tar.gz coreclr-ae991c3a6042256c25d6c82e2714cd41eb14798a.tar.bz2 coreclr-ae991c3a6042256c25d6c82e2714cd41eb14798a.zip | |
Merge pull request #14606 from CarolEidt/Fix14591
LSRA Arm64 consistent reg sets
Diffstat (limited to 'src/jit/target.h')
| -rw-r--r-- | src/jit/target.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/jit/target.h b/src/jit/target.h index 4dafd545a0..1c352d0c1a 100644 --- a/src/jit/target.h +++ b/src/jit/target.h @@ -1599,6 +1599,7 @@ typedef unsigned short regPairNoSmall; // arm: need 12 bits #define REG_VAR_ORDER REG_R9,REG_R10,REG_R11,REG_R12,REG_R13,REG_R14,REG_R15,\ REG_R8,REG_R7,REG_R6,REG_R5,REG_R4,REG_R3,REG_R2,REG_R1,REG_R0,\ REG_R19,REG_R20,REG_R21,REG_R22,REG_R23,REG_R24,REG_R25,REG_R26,REG_R27,REG_R28,\ + REG_IP0,REG_IP1,\ #define REG_VAR_ORDER_FLT REG_V16, REG_V17, REG_V18, REG_V19, \ REG_V20, REG_V21, REG_V22, REG_V23, \ |