1stClassStructs: Replace GT_LDOBJ with GT_OBJ

In preparation for using block nodes in assignments, change GT_LDOBJ to GT_OBJ.
Also, eliminate gtFldTreeList, which was only
being used in a transitory fashion for x87
codegen - instead create the nodes on the fly as needed for stack fp codegen.
Additional minor cleanup.

1 files changed, 12 insertions, 8 deletions

diff --git a/src/jit/simdcodegenxarch.cpp b/src/jit/simdcodegenxarch.cpp
index f419055525..df075f5ca9 100644
--- a/src/jit/simdcodegenxarch.cpp
+++ b/src/jit/simdcodegenxarch.cpp
@@ -537,8 +537,7 @@ CodeGen::genSIMDScalarMove(var_types type, regNumber targetReg, regNumber srcReg
             }
             else
             {
-                instruction ins = getOpForSIMDIntrinsic(SIMDIntrinsicBitwiseXor, type);
-                inst_RV_RV(ins, targetReg, targetReg, targetType, emitTypeSize(targetType));
+                genSIMDZero(targetType, TYP_FLOAT, targetReg);
                 inst_RV_RV(ins_Store(type), targetReg, srcReg);
             }
             break;
@@ -556,6 +555,14 @@ CodeGen::genSIMDScalarMove(var_types type, regNumber targetReg, regNumber srcReg
     }
 }
 
+void
+CodeGen::genSIMDZero(var_types targetType, var_types baseType, regNumber targetReg)
+{
+    // pxor reg, reg
+    instruction ins = getOpForSIMDIntrinsic(SIMDIntrinsicBitwiseXor, baseType);
+    inst_RV_RV(ins, targetReg, targetReg, targetType, emitActualTypeSize(targetType));
+}
+
 //------------------------------------------------------------------------
 // genSIMDIntrinsicInit: Generate code for SIMD Intrinsic Initialize.
 //
@@ -586,9 +593,7 @@ CodeGen::genSIMDIntrinsicInit(GenTreeSIMD* simdNode)
     {
         if (op1->IsZero())
         {   
-            // pxor reg, reg
-            ins = getOpForSIMDIntrinsic(SIMDIntrinsicBitwiseXor, baseType);
-            inst_RV_RV(ins, targetReg, targetReg, targetType, emitActualTypeSize(targetType));
+            genSIMDZero(targetType, baseType, targetReg);
         }
         else if ((baseType == TYP_INT && op1->IsCnsIntOrI() && op1->AsIntConCommon()->IconValue() == 0xffffffff) ||
                  (baseType == TYP_LONG && op1->IsCnsIntOrI() && op1->AsIntConCommon()->IconValue() == 0xffffffffffffffffLL))
@@ -732,12 +737,11 @@ CodeGen::genSIMDIntrinsicInitN(GenTreeSIMD* simdNode)
     assert(genCountBits(simdNode->gtRsvdRegs) == 1);
     regNumber vectorReg = genRegNumFromMask(simdNode->gtRsvdRegs);
 
-    // Zero out vectorReg if we are constructing a vector whose size is not equal to the SIMD vector size.
+    // Zero out vectorReg if we are constructing a vector whose size is not equal to targetType vector size.
     // For example in case of Vector4f we don't need to zero when using SSE2.
     if (compiler->isSubRegisterSIMDType(simdNode))
     {
-        instruction ins = getOpForSIMDIntrinsic(SIMDIntrinsicBitwiseXor, baseType);
-        inst_RV_RV(ins, vectorReg, vectorReg, targetType, emitActualTypeSize(targetType));
+        genSIMDZero(targetType, baseType, vectorReg);
     }
 
     unsigned int baseTypeSize = genTypeSize(baseType);