ARM: Fix reg resolution for doubles

1) When an odd float register becomes free, we may need to add the corresponding (even) double register to `targetRegsReady` (this was the bug)
2) When an even float register becomes free, we can't add it to `targetRegsReady` unless it's other half is also free.

1 files changed, 28 insertions, 3 deletions

diff --git a/src/jit/lsra.cpp b/src/jit/lsra.cpp
index 6727599e48..8bf17effe8 100644
--- a/src/jit/lsra.cpp
+++ b/src/jit/lsra.cpp
@@ -8260,10 +8260,35 @@ void LinearScan::resolveEdge(BasicBlock*      fromBlock,
             location[sourceReg]        = REG_NA;
 
             // Do we have a free targetReg?
-            if (fromReg == sourceReg && source[fromReg] != REG_NA)
+            if (fromReg == sourceReg)
             {
-                regMaskTP fromRegMask = genRegMask(fromReg);
-                targetRegsReady |= fromRegMask;
+                if (source[fromReg] != REG_NA)
+                {
+                    regMaskTP fromRegMask = genRegMask(fromReg);
+                    targetRegsReady |= fromRegMask;
+#ifdef _TARGET_ARM_
+                    if (genIsValidDoubleReg(fromReg))
+                    {
+                        // Ensure that the other half is free.
+                        Interval* otherInterval = sourceIntervals[source[fromReg]];
+                        regNumber upperHalfReg  = REG_NEXT(fromReg);
+                        if ((otherInterval->registerType == TYP_DOUBLE) && (location[upperHalfReg] != REG_NA))
+                        {
+                            targetRegsReady &= ~fromRegMask;
+                        }
+                    }
+                }
+                else if (genIsValidFloatReg(fromReg) && !genIsValidDoubleReg(fromReg))
+                {
+                    // We may have freed up the other half of a double where the lower half
+                    // was already free.
+                    regNumber lowerHalfReg = REG_PREV(fromReg);
+                    if (location[lowerHalfReg] == REG_NA)
+                    {
+                        targetRegsReady |= genRegMask(lowerHalfReg);
+                    }
+#endif // _TARGET_ARM_
+                }
             }
         }
         if (targetRegsToDo != RBM_NONE)