table drive Intel hardware intrinsic

1 files changed, 24 insertions, 84 deletions

diff --git a/src/jit/lowerxarch.cpp b/src/jit/lowerxarch.cpp
index a6f807348d..4169b4a410 100644
--- a/src/jit/lowerxarch.cpp
+++ b/src/jit/lowerxarch.cpp
@@ -2304,96 +2304,36 @@ void Lowering::ContainCheckSIMD(GenTreeSIMD* simdNode)
 //
 void Lowering::ContainCheckHWIntrinsic(GenTreeHWIntrinsic* node)
 {
-    NamedIntrinsic intrinsicID = node->gtHWIntrinsicId;
-    GenTree*       op1         = node->gtGetOp1();
-    GenTree*       op2         = node->gtGetOp2();
-
-    switch (node->gtHWIntrinsicId)
-    {
-        case NI_SSE_Add:
-        case NI_SSE_AddScalar:
-        case NI_SSE_And:
-        case NI_SSE_AndNot:
-        case NI_SSE_CompareEqual:
-        case NI_SSE_CompareEqualScalar:
-        case NI_SSE_CompareGreaterThan:
-        case NI_SSE_CompareGreaterThanScalar:
-        case NI_SSE_CompareGreaterThanOrEqual:
-        case NI_SSE_CompareGreaterThanOrEqualScalar:
-        case NI_SSE_CompareLessThan:
-        case NI_SSE_CompareLessThanScalar:
-        case NI_SSE_CompareLessThanOrEqual:
-        case NI_SSE_CompareLessThanOrEqualScalar:
-        case NI_SSE_CompareNotEqual:
-        case NI_SSE_CompareNotEqualScalar:
-        case NI_SSE_CompareNotGreaterThan:
-        case NI_SSE_CompareNotGreaterThanScalar:
-        case NI_SSE_CompareNotGreaterThanOrEqual:
-        case NI_SSE_CompareNotGreaterThanOrEqualScalar:
-        case NI_SSE_CompareNotLessThan:
-        case NI_SSE_CompareNotLessThanScalar:
-        case NI_SSE_CompareNotLessThanOrEqual:
-        case NI_SSE_CompareNotLessThanOrEqualScalar:
-        case NI_SSE_CompareOrdered:
-        case NI_SSE_CompareOrderedScalar:
-        case NI_SSE_CompareUnordered:
-        case NI_SSE_CompareUnorderedScalar:
-        case NI_SSE_ConvertToVector128SingleScalar:
-        case NI_SSE_Divide:
-        case NI_SSE_DivideScalar:
-        case NI_SSE_Max:
-        case NI_SSE_MaxScalar:
-        case NI_SSE_Min:
-        case NI_SSE_MinScalar:
-        case NI_SSE_Multiply:
-        case NI_SSE_MultiplyScalar:
-        case NI_SSE_Or:
-        case NI_SSE_Subtract:
-        case NI_SSE_SubtractScalar:
-        case NI_SSE_UnpackHigh:
-        case NI_SSE_UnpackLow:
-        case NI_SSE_Xor:
-        case NI_SSE2_Add:
-            if (!comp->getEmitter()->UseVEXEncoding())
-            {
-                // TODO-XArch-CQ: Non-VEX encoded instructions can have both ops contained
-                // TODO-XArch-CQ: Non-VEX encoded instructions require memory ops to be aligned
-                break;
-            }
-            __fallthrough;
+    NamedIntrinsic      intrinsicID = node->gtHWIntrinsicId;
+    HWIntrinsicCategory category    = comp->categoryOfHWIntrinsic(intrinsicID);
+    int                 numArgs     = comp->numArgsOfHWIntrinsic(intrinsicID);
+    GenTree*            op1         = node->gtGetOp1();
+    GenTree*            op2         = node->gtGetOp2();
 
-        case NI_AVX_Add:
-        case NI_AVX2_Add:
+    // TODO-XArch-CQ: Non-VEX encoded instructions can have both ops contained
+    // TODO-XArch-CQ: Non-VEX encoded instructions require memory ops to be aligned
+    if (category == HW_Category_SimpleSIMD && numArgs == 2 && comp->canUseVexEncoding())
+    {
+        if (IsContainableMemoryOp(op2))
         {
-            assert(comp->getEmitter()->UseVEXEncoding());
-
-            if (IsContainableMemoryOp(op2))
-            {
-                MakeSrcContained(node, op2);
-            }
-            else
-            {
-                // TODO-XArch-CQ: Commutative operations can have op1 be contained
-                op2->SetRegOptional();
-            }
-            break;
+            MakeSrcContained(node, op2);
         }
-
-        case NI_SSE_Shuffle:
+        else
         {
-            assert(op1->OperIsList());
-            GenTree* op3 = op1->AsArgList()->Rest()->Rest()->Current();
-
-            if (op3->IsCnsIntOrI())
-            {
-                MakeSrcContained(node, op3);
-            }
-            break;
+            // TODO-XArch-CQ: Commutative operations can have op1 be contained
+            op2->SetRegOptional();
         }
+    }
 
-        default:
-            assert((intrinsicID > NI_HW_INTRINSIC_START) && (intrinsicID < NI_HW_INTRINSIC_END));
-            break;
+    if (NamedIntrinsic == NI_SSE_Shuffle)
+    {
+        assert(op1->OperIsList());
+        GenTree* op3 = op1->AsArgList()->Rest()->Rest()->Current();
+
+        if (op3->IsCnsIntOrI())
+        {
+            MakeSrcContained(node, op3);
+        }
     }
 }
 #endif // FEATURE_HW_INTRINSICS