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authorTanner Gooding <tagoo@outlook.com>2018-02-16 10:30:05 -0800
committerTanner Gooding <tagoo@outlook.com>2018-02-21 22:42:13 -0800
commit987f93399225199bdb3c53e00c9166fb37ca1396 (patch)
tree8fa74fa0e4955a9e4cf63413e988997d0fa7ff69 /src/jit/lowerxarch.cpp
parent7c90b467d072b11c08804a3bb33f3d71f67a6e49 (diff)
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Adding support for the SSE3 and SSSE3 hardware intrinsics
Diffstat (limited to 'src/jit/lowerxarch.cpp')
-rw-r--r--src/jit/lowerxarch.cpp22
1 files changed, 16 insertions, 6 deletions
diff --git a/src/jit/lowerxarch.cpp b/src/jit/lowerxarch.cpp
index 315ca83225..376c3194d3 100644
--- a/src/jit/lowerxarch.cpp
+++ b/src/jit/lowerxarch.cpp
@@ -2409,14 +2409,24 @@ void Lowering::ContainCheckHWIntrinsic(GenTreeHWIntrinsic* node)
break;
}
}
- else if (intrinsicID == NI_SSE_Shuffle) // TODO - change to all IMM intrinsics
+ else if (numArgs == 3)
{
- assert(op1->OperIsList());
- GenTree* op3 = op1->AsArgList()->Rest()->Rest()->Current();
-
- if (op3->IsCnsIntOrI())
+ switch (category)
{
- MakeSrcContained(node, op3);
+ case HW_Category_IMM:
+ {
+ assert(op1->OperIsList());
+ GenTree* op3 = op1->AsArgList()->Rest()->Rest()->Current();
+
+ if (op3->IsCnsIntOrI())
+ {
+ MakeSrcContained(node, op3);
+ }
+ break;
+ }
+
+ default:
+ break;
}
}
}