Move FP DIV/MUL handling to genCodeForBinary

Floating point (SSE) MUL/DIV instructions have the same formats as ADD/SUB but they're handled by genCodeForMul and genCodeForDivMod. At least in the case of division this results in duplicated logic being required in genCodeForDivMod.

1 files changed, 13 insertions, 0 deletions

diff --git a/src/jit/lowerarmarch.cpp b/src/jit/lowerarmarch.cpp
index f91d0865d2..2ad167e28b 100644
--- a/src/jit/lowerarmarch.cpp
+++ b/src/jit/lowerarmarch.cpp
@@ -674,6 +674,19 @@ void Lowering::ContainCheckMul(GenTreeOp* node)
 }
 
 //------------------------------------------------------------------------
+// ContainCheckDivOrMod: determine which operands of a div/mod should be contained.
+//
+// Arguments:
+//    node - the node we care about
+//
+void Lowering::ContainCheckDivOrMod(GenTreeOp* node)
+{
+    assert(node->OperIs(GT_DIV, GT_UDIV));
+
+    // ARM doesn't have a div instruction with an immediate operand
+}
+
+//------------------------------------------------------------------------
 // ContainCheckShiftRotate: Determine whether a mul op's operands should be contained.
 //
 // Arguments: