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| author | Fei Peng <fei.peng@intel.com> | 2017-10-24 14:35:18 -0700 |
|---|---|---|
| committer | Fei Peng <fei.peng@intel.com> | 2017-10-25 15:10:06 -0700 |
| commit | 9dfc3cf5e90a98c204669838b5f9e14baa1d1e3e (patch) | |
| tree | de768274d3ec8f1d9ce05491c987fd26de6a656e /src/jit/instr.h | |
| parent | 15e1472aab7ed42dafde0331ed6cece465a0763d (diff) | |
| download | coreclr-9dfc3cf5e90a98c204669838b5f9e14baa1d1e3e.tar.gz coreclr-9dfc3cf5e90a98c204669838b5f9e14baa1d1e3e.tar.bz2 coreclr-9dfc3cf5e90a98c204669838b5f9e14baa1d1e3e.zip | |
Decoupling SIMD levels from instruction sets
Diffstat (limited to 'src/jit/instr.h')
| -rw-r--r-- | src/jit/instr.h | 16 |
1 files changed, 6 insertions, 10 deletions
diff --git a/src/jit/instr.h b/src/jit/instr.h index eac425634c..ec58f61458 100644 --- a/src/jit/instr.h +++ b/src/jit/instr.h @@ -277,23 +277,19 @@ enum emitAttr : unsigned enum InstructionSet { #ifdef _TARGET_XARCH_ - // Linear order start InstructionSet_ILLEGAL = 0, + // Start linear order SIMD instruction sets + // These ISAs have strictly generation to generation order. InstructionSet_SSE = 1, InstructionSet_SSE2 = 2, InstructionSet_SSE3 = 3, InstructionSet_SSSE3 = 4, InstructionSet_SSE41 = 5, InstructionSet_SSE42 = 6, - InstructionSet_SSE3_4 = 7, // SSE3, SSSE3, SSE4.1 and SSE4.2 instruction set - InstructionSet_AVX = 8, - InstructionSet_AVX2 = 9, - // Linear order end - // TODO - Instruction sets have the linear order only in above area. - // We should no long compare the return value of getSIMDInstructionSet() - // or getFloatingPointInstructionSet() to the InstructionSet values. - // Should refactor SIMD code only to be aware of SIMD feature levels - // (SSE2, SSE3_4, AVX, and AVX2, etc.) rather than concrete ISA. + InstructionSet_AVX = 7, + InstructionSet_AVX2 = 8, + // Reserve values <32 for future SIMD instruction sets (i.e., AVX512), + // End linear order SIMD instruction sets. InstructionSet_AES = 32, InstructionSet_BMI1 = 33, |