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| author | Tanner Gooding <tagoo@outlook.com> | 2017-10-28 09:35:28 -0700 |
|---|---|---|
| committer | Tanner Gooding <tagoo@outlook.com> | 2018-01-14 17:37:43 -0800 |
| commit | 7ba1bf921700a66ee2e45ce5f706b3366ee493ba (patch) | |
| tree | 8f9c449fe0b80a9dc19317b22786281161e823c5 /src/jit/emitfmtsxarch.h | |
| parent | 2f3fa55c05bd4c2c60eb627d41634efaf46d20d3 (diff) | |
| download | coreclr-7ba1bf921700a66ee2e45ce5f706b3366ee493ba.tar.gz coreclr-7ba1bf921700a66ee2e45ce5f706b3366ee493ba.tar.bz2 coreclr-7ba1bf921700a66ee2e45ce5f706b3366ee493ba.zip | |
Adding SSE4.1 intrinsic support for Round, Ceiling, and Floor.
Diffstat (limited to 'src/jit/emitfmtsxarch.h')
| -rw-r--r-- | src/jit/emitfmtsxarch.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/jit/emitfmtsxarch.h b/src/jit/emitfmtsxarch.h index f00e64fb20..d0aef507e0 100644 --- a/src/jit/emitfmtsxarch.h +++ b/src/jit/emitfmtsxarch.h @@ -122,6 +122,7 @@ IF_DEF(MRD_OFF, IS_GM_RD, DSP) // offset mem IF_DEF(RRD_MRD, IS_GM_RD|IS_R1_RD, DSP) // read reg , read [mem] IF_DEF(RWR_MRD, IS_GM_RD|IS_R1_WR, DSP) // write reg , read [mem] IF_DEF(RRW_MRD, IS_GM_RD|IS_R1_RW, DSP) // r/w reg , read [mem] +IF_DEF(RRW_MRD_CNS, IS_GM_RD|IS_R1_RW, DSP_CNS) // r/w reg , read [mem], const IF_DEF(RWR_RRD_MRD, IS_GM_RD|IS_R1_WR|IS_R2_RD, DSP) // write reg , read reg2 , read [mem] IF_DEF(RWR_MRD_OFF, IS_GM_RD|IS_R1_WR, DSP) // write reg , offset mem @@ -147,6 +148,7 @@ IF_DEF(SRW, IS_SF_RW, NONE) // r/w [stk] IF_DEF(RRD_SRD, IS_SF_RD|IS_R1_RD, NONE) // read reg , read [stk] IF_DEF(RWR_SRD, IS_SF_RD|IS_R1_WR, NONE) // write reg , read [stk] IF_DEF(RRW_SRD, IS_SF_RD|IS_R1_RW, NONE) // r/w reg , read [stk] +IF_DEF(RRW_SRD_CNS, IS_SF_RD|IS_R1_RW, CNS ) // r/w reg , read [stk], const IF_DEF(RWR_RRD_SRD, IS_SF_RD|IS_R1_WR|IS_R2_RD, NONE) // write reg , read reg2, read [stk] @@ -172,6 +174,7 @@ IF_DEF(ARW, IS_AM_RW, AMD ) // r/w [adr] IF_DEF(RRD_ARD, IS_AM_RD|IS_R1_RD, AMD ) // read reg , read [adr] IF_DEF(RWR_ARD, IS_AM_RD|IS_R1_WR, AMD ) // write reg , read [adr] IF_DEF(RRW_ARD, IS_AM_RD|IS_R1_RW, AMD ) // r/w reg , read [adr] +IF_DEF(RRW_ARD_CNS, IS_AM_RD|IS_R1_RW, AMD_CNS) // r/w reg , read [adr], const IF_DEF(RWR_RRD_ARD, IS_AM_RD|IS_R1_WR|IS_R2_RD, AMD ) // write reg , read reg2, read [adr] |