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| author | Tanner Gooding <tagoo@outlook.com> | 2018-06-06 18:24:04 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-06-06 18:24:04 -0700 |
| commit | f7993ddfc19ccce311df69b32f675bd076935e7f (patch) | |
| tree | 87921d580a0a4f22a7838aa426488f73347ce2ee /src/jit/emitfmtsxarch.h | |
| parent | dce3234ecd057e7332140e137e23b0fe2aca9919 (diff) | |
| download | coreclr-f7993ddfc19ccce311df69b32f675bd076935e7f.tar.gz coreclr-f7993ddfc19ccce311df69b32f675bd076935e7f.tar.bz2 coreclr-f7993ddfc19ccce311df69b32f675bd076935e7f.zip | |
Adding containment support for more x86 hardware intrinsics (#18297)
* Adding containment support to one-operand scalar HWIntrinsics (x86)
* Adding containment support to two-operand imm HWIntrinsics (x86)
* Adding containment support to three-operand imm HWIntrinsics (x86)
* Updating hwintrinsiccodegenxarch to properly mask Sse41.Insert for TYP_FLOAT
* Updating the Sse41.Insert tests for TYP_FLOAT
* Adding containment support for Sse2.CompareLessThan and BlendVariable (Sse41/Avx/Avx2)
* Fixing `genHWIntrinsic_R_RM_I` to call `emitIns_SIMD_R_R_I`, rather than `emitIns_R_R_I`
* Updating emitOutputSV to not modify the code for IF_RWR_RRD_SRD_CNS
* Cleaning up some of the emitxarch code.
* Moving roundps and roundpd into the IsDstSrcImm check
Diffstat (limited to 'src/jit/emitfmtsxarch.h')
| -rw-r--r-- | src/jit/emitfmtsxarch.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/jit/emitfmtsxarch.h b/src/jit/emitfmtsxarch.h index a2814f86ce..84bc0f8aec 100644 --- a/src/jit/emitfmtsxarch.h +++ b/src/jit/emitfmtsxarch.h @@ -129,6 +129,7 @@ IF_DEF(RRW_MRD_CNS, IS_GM_RD|IS_R1_RW, DSP_CNS) // r/w reg , read [ IF_DEF(RWR_RRD_MRD, IS_GM_RD|IS_R1_WR|IS_R2_RD, DSP) // write reg , read reg2 , read [mem] IF_DEF(RWR_MRD_CNS, IS_GM_RD|IS_R1_WR, DSP_CNS) // write reg , read [mem], const IF_DEF(RWR_RRD_MRD_CNS, IS_GM_RD|IS_R1_WR|IS_R2_RD, DSP_CNS) // write reg , read reg2 , read [mem], const +IF_DEF(RWR_RRD_MRD_RRD, IS_GM_RD|IS_R1_WR|IS_R2_RD|IS_R3_RD, DSP_CNS) // write reg , read reg2 , read [mem], read reg3 IF_DEF(RWR_MRD_OFF, IS_GM_RD|IS_R1_WR, DSP) // write reg , offset mem IF_DEF(MRD_RRD, IS_GM_RD|IS_R1_RD, DSP) // read [mem], read reg @@ -159,6 +160,7 @@ IF_DEF(RRW_SRD_CNS, IS_SF_RD|IS_R1_RW, CNS ) // r/w reg , read [ IF_DEF(RWR_RRD_SRD, IS_SF_RD|IS_R1_WR|IS_R2_RD, NONE) // write reg , read reg2, read [stk] IF_DEF(RWR_SRD_CNS, IS_SF_RD|IS_R1_WR, CNS ) // write reg , read [stk], const IF_DEF(RWR_RRD_SRD_CNS, IS_SF_RD|IS_R1_WR|IS_R2_RD, CNS ) // write reg , read reg2, read [stk], const +IF_DEF(RWR_RRD_SRD_RRD, IS_SF_RD|IS_R1_WR|IS_R2_RD|IS_R3_RD, CNS ) // write reg , read reg2, read [stk], read reg3 IF_DEF(SRD_RRD, IS_SF_RD|IS_R1_RD, NONE) // read [stk], read reg IF_DEF(SWR_RRD, IS_SF_WR|IS_R1_RD, NONE) // write [stk], read reg @@ -187,6 +189,7 @@ IF_DEF(RRW_ARD_CNS, IS_AM_RD|IS_R1_RW, AMD_CNS) // r/w reg , read [ IF_DEF(RWR_RRD_ARD, IS_AM_RD|IS_R1_WR|IS_R2_RD, AMD ) // write reg , read reg2, read [adr] IF_DEF(RWR_ARD_CNS, IS_AM_RD|IS_R1_WR, AMD_CNS) // write reg , read [adr], const IF_DEF(RWR_RRD_ARD_CNS, IS_AM_RD|IS_R1_WR|IS_R2_RD, AMD_CNS) // write reg , read reg2, read [adr], const +IF_DEF(RWR_RRD_ARD_RRD, IS_AM_RD|IS_R1_WR|IS_R2_RD|IS_R3_RD, AMD_CNS) // write reg , read reg2, read [adr], read reg3 IF_DEF(ARD_RRD, IS_AM_RD|IS_R1_RD, AMD ) // read [adr], read reg IF_DEF(AWR_RRD, IS_AM_WR|IS_R1_RD, AMD ) // write [adr], read reg |