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| author | Kyungwoo Lee <kyulee@microsoft.com> | 2016-04-29 10:29:28 -0700 |
|---|---|---|
| committer | Kyungwoo Lee <kyulee@microsoft.com> | 2016-04-29 14:52:46 -0700 |
| commit | 45798f661f8c8c042f3582cde8b611d1c9c7343f (patch) | |
| tree | 0d75dad9935f95c5bf4bd309899a37456e4478bd /src/jit/emitfmtsarm64.h | |
| parent | 601b1051c1022d5f764224e35be59f02a6074ad0 (diff) | |
| download | coreclr-45798f661f8c8c042f3582cde8b611d1c9c7343f.tar.gz coreclr-45798f661f8c8c042f3582cde8b611d1c9c7343f.tar.bz2 coreclr-45798f661f8c8c042f3582cde8b611d1c9c7343f.zip | |
ARM64: Enabling Crossgen End-to-End Mscorlib
Fixes https://github.com/dotnet/coreclr/issues/4350
Fixes https://github.com/dotnet/coreclr/issues/4615
This is a bit large change across VM/Zap/JIT to properly support crossgen
scenario.
1. Fix incorrect `ldr` encoding with size.
2. Enforce JIT data following JIT code per method by allocating them together.
This guarantees correct PC-relative encoding for such constant data access
without fix-up.
3. For the general fix-up data acceess, use `adrp/add` instruction pairs with fix-ups.
Two more relocations types are implemented in all sides.
4. Interface dispatch stub is now implemented which is needed for
interface call for crossgen.
I've verified hello world runs with mscorlib.ni.dll.
Diffstat (limited to 'src/jit/emitfmtsarm64.h')
| -rw-r--r-- | src/jit/emitfmtsarm64.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/jit/emitfmtsarm64.h b/src/jit/emitfmtsarm64.h index 722e48c580..06cde03f8c 100644 --- a/src/jit/emitfmtsarm64.h +++ b/src/jit/emitfmtsarm64.h @@ -121,7 +121,7 @@ IF_DEF(BI_1B, IS_NONE, JMP) // BI_1B B.......bbbbbiii IF_DEF(BR_1A, IS_NONE, CALL) // BR_1A ................ ......nnnnn..... Rn ret IF_DEF(BR_1B, IS_NONE, CALL) // BR_1B ................ ......nnnnn..... Rn br blr -IF_DEF(LS_1A, IS_NONE, JMP) // LS_1A .X......iiiiiiii iiiiiiiiiiittttt Rt PC imm(1MB) +IF_DEF(LS_1A, IS_NONE, JMP) // LS_1A XX...V..iiiiiiii iiiiiiiiiiittttt Rt PC imm(1MB) IF_DEF(LS_2A, IS_NONE, NONE) // LS_2A .X.......X...... ......nnnnnttttt Rt Rn IF_DEF(LS_2B, IS_NONE, NONE) // LS_2B .X.......Xiiiiii iiiiiinnnnnttttt Rt Rn imm(0-4095) IF_DEF(LS_2C, IS_NONE, NONE) // LS_2C .X.......X.iiiii iiiiP.nnnnnttttt Rt Rn imm(-256..+255) pre/post inc |